Heterogeneous Tiles (#550)
Fundamental new features: * Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces. * Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile. * Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile. * Defined RocketCoreParams: All the parameters that can be varied per-core. * Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes. * Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created. * Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little. * Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support. Additional changes that got rolled in along the way: * rocket: Fix critical path through BTB for I$ index bits > pgIdxBits * coreplex: tiles connected via :=* * groundtest: updated to use TileParams * tilelink: cache cork requirements are relaxed to allow more cacheless masters
This commit is contained in:
Henry Cook
GitHub
677
src/main/scala/rocket/CSR.scala
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677
src/main/scala/rocket/CSR.scala
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@ -0,0 +1,677 @@
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// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package rocket
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import Chisel._
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import Instructions._
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import config._
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import tile._
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import uncore.devices._
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import util._
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import Chisel.ImplicitConversions._
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class MStatus extends Bundle {
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// not truly part of mstatus, but convenient
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val debug = Bool()
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val isa = UInt(width = 32)
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val prv = UInt(width = PRV.SZ) // not truly part of mstatus, but convenient
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val sd = Bool()
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val zero3 = UInt(width = 31)
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val sd_rv32 = Bool()
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val zero2 = UInt(width = 2)
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val vm = UInt(width = 5)
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val zero1 = UInt(width = 4)
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val mxr = Bool()
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val pum = Bool()
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val mprv = Bool()
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val xs = UInt(width = 2)
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val fs = UInt(width = 2)
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val mpp = UInt(width = 2)
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val hpp = UInt(width = 2)
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val spp = UInt(width = 1)
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val mpie = Bool()
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val hpie = Bool()
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val spie = Bool()
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val upie = Bool()
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val mie = Bool()
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val hie = Bool()
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val sie = Bool()
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val uie = Bool()
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}
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class DCSR extends Bundle {
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val xdebugver = UInt(width = 2)
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val ndreset = Bool()
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val fullreset = Bool()
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val zero3 = UInt(width = 12)
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val ebreakm = Bool()
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val ebreakh = Bool()
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val ebreaks = Bool()
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val ebreaku = Bool()
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val zero2 = Bool()
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val stopcycle = Bool()
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val stoptime = Bool()
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val cause = UInt(width = 3)
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val debugint = Bool()
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val zero1 = Bool()
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val halt = Bool()
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val step = Bool()
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val prv = UInt(width = PRV.SZ)
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}
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class MIP extends Bundle {
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val rocc = Bool()
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val meip = Bool()
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val heip = Bool()
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val seip = Bool()
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val ueip = Bool()
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val mtip = Bool()
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val htip = Bool()
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val stip = Bool()
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val utip = Bool()
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val msip = Bool()
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val hsip = Bool()
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val ssip = Bool()
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val usip = Bool()
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}
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class PTBR(implicit p: Parameters) extends CoreBundle()(p) {
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require(maxPAddrBits - pgIdxBits + asIdBits <= xLen)
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val asid = UInt(width = asIdBits)
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val ppn = UInt(width = maxPAddrBits - pgIdxBits)
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}
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object PRV
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{
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val SZ = 2
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val U = 0
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val S = 1
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val H = 2
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val M = 3
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}
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object CSR
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{
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// commands
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val SZ = 3
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def X = BitPat.dontCare(SZ)
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def N = UInt(0,SZ)
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def W = UInt(1,SZ)
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def S = UInt(2,SZ)
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def C = UInt(3,SZ)
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def I = UInt(4,SZ)
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def R = UInt(5,SZ)
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val ADDRSZ = 12
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def debugIntCause = new MIP().getWidth
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def debugTriggerCause = {
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require(debugIntCause >= Causes.all.max)
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debugIntCause
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}
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val firstCtr = CSRs.cycle
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val firstHPM = 3
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val firstHPC = CSRs.cycle + firstHPM
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val firstHPE = CSRs.mucounteren + firstHPM
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val firstMHPC = CSRs.mcycle + firstHPM
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val nHPM = 29
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val nCtr = firstHPM + nHPM
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}
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class CSRFileIO(implicit p: Parameters) extends CoreBundle
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with HasRocketCoreParameters {
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val interrupts = new TileInterrupts().asInput
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val hartid = UInt(INPUT, xLen)
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val rw = new Bundle {
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val addr = UInt(INPUT, CSR.ADDRSZ)
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val cmd = Bits(INPUT, CSR.SZ)
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val rdata = Bits(OUTPUT, xLen)
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val wdata = Bits(INPUT, xLen)
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}
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val csr_stall = Bool(OUTPUT)
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val csr_xcpt = Bool(OUTPUT)
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val eret = Bool(OUTPUT)
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val singleStep = Bool(OUTPUT)
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val status = new MStatus().asOutput
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val ptbr = new PTBR().asOutput
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val evec = UInt(OUTPUT, vaddrBitsExtended)
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val exception = Bool(INPUT)
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val retire = UInt(INPUT, log2Up(1+retireWidth))
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val custom_mrw_csrs = Vec(nCustomMrwCsrs, UInt(INPUT, xLen))
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val cause = UInt(INPUT, xLen)
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val pc = UInt(INPUT, vaddrBitsExtended)
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val badaddr = UInt(INPUT, vaddrBitsExtended)
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val fatc = Bool(OUTPUT)
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val time = UInt(OUTPUT, xLen)
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val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
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val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
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val rocc_interrupt = Bool(INPUT)
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val interrupt = Bool(OUTPUT)
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val interrupt_cause = UInt(OUTPUT, xLen)
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val bp = Vec(nBreakpoints, new BP).asOutput
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val events = Vec(nPerfEvents, Bool()).asInput
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}
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class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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with HasRocketCoreParameters {
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val io = new CSRFileIO
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val reset_mstatus = Wire(init=new MStatus().fromBits(0))
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reset_mstatus.mpp := PRV.M
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reset_mstatus.prv := PRV.M
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val reg_mstatus = Reg(init=reset_mstatus)
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val new_prv = Wire(init = reg_mstatus.prv)
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reg_mstatus.prv := legalizePrivilege(new_prv)
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val reset_dcsr = Wire(init=new DCSR().fromBits(0))
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reset_dcsr.xdebugver := 1
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reset_dcsr.prv := PRV.M
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val reg_dcsr = Reg(init=reset_dcsr)
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val (supported_interrupts, delegable_interrupts) = {
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val sup = Wire(init=new MIP().fromBits(0))
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sup.ssip := Bool(usingVM)
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sup.msip := true
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sup.stip := Bool(usingVM)
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sup.mtip := true
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sup.meip := true
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sup.seip := Bool(usingVM)
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sup.rocc := usingRoCC
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val del = Wire(init=sup)
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del.msip := false
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del.mtip := false
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del.meip := false
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(sup.asUInt, del.asUInt)
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}
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val delegable_exceptions = UInt(Seq(
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Causes.misaligned_fetch,
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Causes.fault_fetch,
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Causes.breakpoint,
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Causes.fault_load,
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Causes.fault_store,
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Causes.user_ecall).map(1 << _).sum)
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val exception = io.exception || io.csr_xcpt
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val reg_debug = Reg(init=Bool(false))
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val reg_dpc = Reg(UInt(width = vaddrBitsExtended))
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val reg_dscratch = Reg(UInt(width = xLen))
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val reg_singleStepped = Reg(Bool())
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when (io.retire(0) || exception) { reg_singleStepped := true }
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when (!io.singleStep) { reg_singleStepped := false }
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assert(!io.singleStep || io.retire <= UInt(1))
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assert(!reg_singleStepped || io.retire === UInt(0))
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val reg_tselect = Reg(UInt(width = log2Up(nBreakpoints)))
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val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
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val reg_mie = Reg(UInt(width = xLen))
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val reg_mideleg = Reg(UInt(width = xLen))
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val reg_medeleg = Reg(UInt(width = xLen))
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val reg_mip = Reg(new MIP)
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val reg_mepc = Reg(UInt(width = vaddrBitsExtended))
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val reg_mcause = Reg(Bits(width = xLen))
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val reg_mbadaddr = Reg(UInt(width = vaddrBitsExtended))
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val reg_mscratch = Reg(Bits(width = xLen))
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val mtvecWidth = paddrBits min xLen
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val reg_mtvec = mtvecInit match {
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case Some(addr) => Reg(init=UInt(addr, mtvecWidth))
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case None => Reg(UInt(width = mtvecWidth))
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}
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val reg_mucounteren = Reg(UInt(width = 32))
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val reg_mscounteren = Reg(UInt(width = 32))
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val delegable_counters = (BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1
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val reg_sepc = Reg(UInt(width = vaddrBitsExtended))
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val reg_scause = Reg(Bits(width = xLen))
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val reg_sbadaddr = Reg(UInt(width = vaddrBitsExtended))
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val reg_sscratch = Reg(Bits(width = xLen))
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val reg_stvec = Reg(UInt(width = vaddrBits))
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val reg_sptbr = Reg(new PTBR)
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val reg_wfi = Reg(init=Bool(false))
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val reg_fflags = Reg(UInt(width = 5))
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val reg_frm = Reg(UInt(width = 3))
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val reg_instret = WideCounter(64, io.retire)
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val reg_cycle = if (enableCommitLog) reg_instret else WideCounter(64)
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val reg_hpmevent = Seq.fill(nPerfCounters)(if (nPerfEvents > 1) Reg(UInt(width = log2Ceil(nPerfEvents))) else UInt(0))
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val reg_hpmcounter = reg_hpmevent.map(e => WideCounter(64, ((UInt(0) +: io.events): Seq[UInt])(e)))
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val mip = Wire(init=reg_mip)
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mip.rocc := io.rocc_interrupt
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val read_mip = mip.asUInt & supported_interrupts
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val pending_interrupts = read_mip & reg_mie
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val m_interrupts = Mux(!reg_debug && (reg_mstatus.prv < PRV.M || (reg_mstatus.prv === PRV.M && reg_mstatus.mie)), pending_interrupts & ~reg_mideleg, UInt(0))
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val s_interrupts = Mux(!reg_debug && (reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie)), pending_interrupts & reg_mideleg, UInt(0))
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val all_interrupts = m_interrupts | s_interrupts
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val interruptMSB = BigInt(1) << (xLen-1)
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val interruptCause = UInt(interruptMSB) + PriorityEncoder(all_interrupts)
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io.interrupt := all_interrupts.orR && !io.singleStep || reg_singleStepped
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io.interrupt_cause := interruptCause
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io.bp := reg_bp take nBreakpoints
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// debug interrupts are only masked by being in debug mode
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when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) {
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io.interrupt := true
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io.interrupt_cause := UInt(interruptMSB) + CSR.debugIntCause
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}
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val system_insn = io.rw.cmd === CSR.I
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val cpu_ren = io.rw.cmd =/= CSR.N && !system_insn
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val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R
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val isaMaskString =
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(if (usingMulDiv) "M" else "") +
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(if (usingAtomics) "A" else "") +
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(if (usingFPU) "F" else "") +
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(if (usingFPU && xLen > 32) "D" else "") +
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(if (usingCompressed) "C" else "") +
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(if (usingRoCC) "X" else "")
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val isaString = "I" + isaMaskString +
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(if (usingVM) "S" else "") +
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(if (usingUser) "U" else "")
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val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString)
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val reg_misa = Reg(init=UInt(isaMax))
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val read_mstatus = io.status.asUInt()(xLen-1,0)
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val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
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CSRs.tselect -> reg_tselect,
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CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt,
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CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen),
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CSRs.mimpid -> UInt(0),
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CSRs.marchid -> UInt(0),
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CSRs.mvendorid -> UInt(0),
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CSRs.mcycle -> reg_cycle,
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CSRs.minstret -> reg_instret,
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CSRs.misa -> reg_misa,
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CSRs.mstatus -> read_mstatus,
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CSRs.mtvec -> reg_mtvec,
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CSRs.mip -> read_mip,
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CSRs.mie -> reg_mie,
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CSRs.mideleg -> reg_mideleg,
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CSRs.medeleg -> reg_medeleg,
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CSRs.mscratch -> reg_mscratch,
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CSRs.mepc -> reg_mepc.sextTo(xLen),
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CSRs.mbadaddr -> reg_mbadaddr.sextTo(xLen),
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CSRs.mcause -> reg_mcause,
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CSRs.mhartid -> io.hartid)
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val debug_csrs = collection.immutable.ListMap(
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CSRs.dcsr -> reg_dcsr.asUInt,
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CSRs.dpc -> reg_dpc.asUInt,
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CSRs.dscratch -> reg_dscratch.asUInt)
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val fp_csrs = collection.immutable.ListMap(
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CSRs.fflags -> reg_fflags,
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CSRs.frm -> reg_frm,
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CSRs.fcsr -> Cat(reg_frm, reg_fflags))
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if (usingDebug)
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read_mapping ++= debug_csrs
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if (usingFPU)
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read_mapping ++= fp_csrs
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for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, UInt(0))
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zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, UInt(0))) zipWithIndex) {
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read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN
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read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN
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if (usingUser) read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN
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}
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if (usingVM) {
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val read_sie = reg_mie & reg_mideleg
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val read_sip = read_mip & reg_mideleg
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val read_sstatus = Wire(init=io.status)
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read_sstatus.vm := 0
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read_sstatus.mprv := 0
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read_sstatus.mpp := 0
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read_sstatus.hpp := 0
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read_sstatus.mpie := 0
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read_sstatus.hpie := 0
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read_sstatus.mie := 0
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read_sstatus.hie := 0
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read_mapping += CSRs.sstatus -> (read_sstatus.asUInt())(xLen-1,0)
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read_mapping += CSRs.sip -> read_sip.asUInt
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read_mapping += CSRs.sie -> read_sie.asUInt
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read_mapping += CSRs.sscratch -> reg_sscratch
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read_mapping += CSRs.scause -> reg_scause
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read_mapping += CSRs.sbadaddr -> reg_sbadaddr.sextTo(xLen)
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read_mapping += CSRs.sptbr -> reg_sptbr.asUInt
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read_mapping += CSRs.sepc -> reg_sepc.sextTo(xLen)
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read_mapping += CSRs.stvec -> reg_stvec.sextTo(xLen)
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read_mapping += CSRs.mscounteren -> reg_mscounteren
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}
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if (usingUser) {
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read_mapping += CSRs.mucounteren -> reg_mucounteren
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read_mapping += CSRs.cycle -> reg_cycle
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read_mapping += CSRs.instret -> reg_instret
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}
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if (xLen == 32) {
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read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
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read_mapping += CSRs.minstreth -> (reg_instret >> 32)
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if (usingUser) {
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read_mapping += CSRs.cycleh -> (reg_cycle >> 32)
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read_mapping += CSRs.instreth -> (reg_instret >> 32)
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}
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}
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for (i <- 0 until nCustomMrwCsrs) {
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val addr = 0xff0 + i
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require(addr < (1 << CSR.ADDRSZ))
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require(!read_mapping.contains(addr), "custom MRW CSR address " + i + " is already in use")
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read_mapping += addr -> io.custom_mrw_csrs(i)
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}
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val decoded_addr = read_mapping map { case (k, v) => k -> (io.rw.addr === k) }
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val addr_valid = decoded_addr.values.reduce(_||_)
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val fp_csr = if (usingFPU) decoded_addr.filterKeys(fp_csrs contains _ ).values reduce(_||_) else Bool(false)
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val hpm_csr = if (usingUser) io.rw.addr >= CSR.firstCtr && io.rw.addr < CSR.firstCtr + CSR.nCtr else Bool(false)
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val hpm_en = reg_debug || reg_mstatus.prv === PRV.M ||
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(reg_mstatus.prv === PRV.S && reg_mscounteren(io.rw.addr(log2Ceil(CSR.nCtr)-1, 0))) ||
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(reg_mstatus.prv === PRV.U && reg_mucounteren(io.rw.addr(log2Ceil(CSR.nCtr)-1, 0)))
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val csr_addr_priv = io.rw.addr(9,8)
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val debug_csr_mask = 0x090 // only debug CSRs have address bits 7 and 4 set
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require((read_mapping -- debug_csrs.keys).keys.forall(x => (x & debug_csr_mask) != debug_csr_mask))
|
||||
require(debug_csrs.keys.forall(x => (x & debug_csr_mask) == debug_csr_mask))
|
||||
val csr_debug = Bool(usingDebug) && (io.rw.addr & debug_csr_mask) === debug_csr_mask
|
||||
val priv_sufficient = reg_debug || (!csr_debug && reg_mstatus.prv >= csr_addr_priv)
|
||||
val read_only = io.rw.addr(11,10).andR
|
||||
val wen = cpu_wen && priv_sufficient && !read_only
|
||||
|
||||
val wdata = (Mux(io.rw.cmd.isOneOf(CSR.S, CSR.C), io.rw.rdata, UInt(0)) |
|
||||
Mux(io.rw.cmd =/= CSR.C, io.rw.wdata, UInt(0))) &
|
||||
~Mux(io.rw.cmd === CSR.C, io.rw.wdata, UInt(0))
|
||||
|
||||
val do_system_insn = priv_sufficient && system_insn
|
||||
val opcode = UInt(1) << io.rw.addr(2,0)
|
||||
val insn_call = do_system_insn && opcode(0)
|
||||
val insn_break = do_system_insn && opcode(1)
|
||||
val insn_ret = do_system_insn && opcode(2)
|
||||
val insn_sfence_vm = do_system_insn && opcode(4)
|
||||
val insn_wfi = do_system_insn && opcode(5)
|
||||
|
||||
io.csr_xcpt := (cpu_wen && read_only) ||
|
||||
(cpu_ren && (!priv_sufficient || !addr_valid || (hpm_csr && !hpm_en) || (fp_csr && !(io.status.fs.orR && reg_misa('f'-'a'))))) ||
|
||||
(system_insn && !priv_sufficient) ||
|
||||
insn_call || insn_break
|
||||
|
||||
when (insn_wfi) { reg_wfi := true }
|
||||
when (pending_interrupts.orR) { reg_wfi := false }
|
||||
|
||||
val cause =
|
||||
Mux(!io.csr_xcpt, io.cause,
|
||||
Mux(insn_call, reg_mstatus.prv + Causes.user_ecall,
|
||||
Mux[UInt](insn_break, Causes.breakpoint, Causes.illegal_instruction)))
|
||||
val cause_lsbs = cause(log2Up(xLen)-1,0)
|
||||
val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause
|
||||
val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause
|
||||
val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
|
||||
val trapToDebug = Bool(usingDebug) && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug)
|
||||
val delegate = Bool(usingVM) && reg_mstatus.prv < PRV.M && Mux(cause(xLen-1), reg_mideleg(cause_lsbs), reg_medeleg(cause_lsbs))
|
||||
val debugTVec = Mux(reg_debug, UInt(0x808), UInt(0x800))
|
||||
val tvec = Mux(trapToDebug, debugTVec, Mux(delegate, reg_stvec.sextTo(vaddrBitsExtended), reg_mtvec))
|
||||
val epc = Mux(csr_debug, reg_dpc, Mux(Bool(usingVM) && !csr_addr_priv(1), reg_sepc, reg_mepc))
|
||||
io.fatc := insn_sfence_vm
|
||||
io.evec := Mux(exception, tvec, epc)
|
||||
io.ptbr := reg_sptbr
|
||||
io.eret := insn_ret
|
||||
io.singleStep := reg_dcsr.step && !reg_debug
|
||||
io.status := reg_mstatus
|
||||
io.status.sd := io.status.fs.andR || io.status.xs.andR
|
||||
io.status.debug := reg_debug
|
||||
io.status.isa := reg_misa
|
||||
if (xLen == 32)
|
||||
io.status.sd_rv32 := io.status.sd
|
||||
|
||||
when (exception) {
|
||||
val epc = ~(~io.pc | (coreInstBytes-1))
|
||||
val pie = read_mstatus(reg_mstatus.prv)
|
||||
|
||||
val write_badaddr = cause isOneOf (Causes.breakpoint,
|
||||
Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
|
||||
Causes.fault_load, Causes.fault_store, Causes.fault_fetch)
|
||||
|
||||
when (trapToDebug) {
|
||||
reg_debug := true
|
||||
reg_dpc := epc
|
||||
reg_dcsr.cause := Mux(reg_singleStepped, 4, Mux(causeIsDebugInt, 3, Mux[UInt](causeIsDebugTrigger, 2, 1)))
|
||||
reg_dcsr.prv := trimPrivilege(reg_mstatus.prv)
|
||||
}.elsewhen (delegate) {
|
||||
reg_sepc := formEPC(epc)
|
||||
reg_scause := cause
|
||||
when (write_badaddr) { reg_sbadaddr := io.badaddr }
|
||||
reg_mstatus.spie := pie
|
||||
reg_mstatus.spp := reg_mstatus.prv
|
||||
reg_mstatus.sie := false
|
||||
new_prv := PRV.S
|
||||
}.otherwise {
|
||||
reg_mepc := formEPC(epc)
|
||||
reg_mcause := cause
|
||||
when (write_badaddr) { reg_mbadaddr := io.badaddr }
|
||||
reg_mstatus.mpie := pie
|
||||
reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
|
||||
reg_mstatus.mie := false
|
||||
new_prv := PRV.M
|
||||
}
|
||||
}
|
||||
|
||||
when (insn_ret) {
|
||||
when (Bool(usingVM) && !csr_addr_priv(1)) {
|
||||
when (reg_mstatus.spp.toBool) { reg_mstatus.sie := reg_mstatus.spie }
|
||||
reg_mstatus.spie := true
|
||||
reg_mstatus.spp := PRV.U
|
||||
new_prv := reg_mstatus.spp
|
||||
}.elsewhen (csr_debug) {
|
||||
new_prv := reg_dcsr.prv
|
||||
reg_debug := false
|
||||
}.otherwise {
|
||||
when (reg_mstatus.mpp(1)) { reg_mstatus.mie := reg_mstatus.mpie }
|
||||
.elsewhen (Bool(usingVM) && reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie }
|
||||
reg_mstatus.mpie := true
|
||||
reg_mstatus.mpp := legalizePrivilege(PRV.U)
|
||||
new_prv := reg_mstatus.mpp
|
||||
}
|
||||
}
|
||||
|
||||
assert(PopCount(insn_ret :: io.exception :: io.csr_xcpt :: Nil) <= 1, "these conditions must be mutually exclusive")
|
||||
|
||||
io.time := reg_cycle
|
||||
io.csr_stall := reg_wfi
|
||||
|
||||
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
|
||||
|
||||
io.fcsr_rm := reg_frm
|
||||
when (io.fcsr_flags.valid) {
|
||||
reg_fflags := reg_fflags | io.fcsr_flags.bits
|
||||
}
|
||||
|
||||
when (wen) {
|
||||
when (decoded_addr(CSRs.mstatus)) {
|
||||
val new_mstatus = new MStatus().fromBits(wdata)
|
||||
reg_mstatus.mie := new_mstatus.mie
|
||||
reg_mstatus.mpie := new_mstatus.mpie
|
||||
|
||||
if (usingUser) {
|
||||
reg_mstatus.mprv := new_mstatus.mprv
|
||||
reg_mstatus.mpp := trimPrivilege(new_mstatus.mpp)
|
||||
if (usingVM) {
|
||||
reg_mstatus.mxr := new_mstatus.mxr
|
||||
reg_mstatus.pum := new_mstatus.pum
|
||||
reg_mstatus.spp := new_mstatus.spp
|
||||
reg_mstatus.spie := new_mstatus.spie
|
||||
reg_mstatus.sie := new_mstatus.sie
|
||||
}
|
||||
}
|
||||
|
||||
if (usingVM) {
|
||||
require(if (xLen == 32) pgLevels == 2 else pgLevels > 2 && pgLevels < 6)
|
||||
val vm_on = 6 + pgLevels // TODO Sv48 support should imply Sv39 support
|
||||
when (new_mstatus.vm === 0) { reg_mstatus.vm := 0 }
|
||||
when (new_mstatus.vm === vm_on) { reg_mstatus.vm := vm_on }
|
||||
}
|
||||
if (usingVM || usingFPU) reg_mstatus.fs := Fill(2, new_mstatus.fs.orR)
|
||||
if (usingRoCC) reg_mstatus.xs := Fill(2, new_mstatus.xs.orR)
|
||||
}
|
||||
when (decoded_addr(CSRs.misa)) {
|
||||
val mask = UInt(isaStringToMask(isaMaskString))
|
||||
val f = wdata('f' - 'a')
|
||||
reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask
|
||||
}
|
||||
when (decoded_addr(CSRs.mip)) {
|
||||
val new_mip = new MIP().fromBits(wdata)
|
||||
if (usingVM) {
|
||||
reg_mip.ssip := new_mip.ssip
|
||||
reg_mip.stip := new_mip.stip
|
||||
}
|
||||
}
|
||||
when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts }
|
||||
when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) }
|
||||
when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
|
||||
if (mtvecWritable)
|
||||
when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata >> 2 << 2 }
|
||||
when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
|
||||
when (decoded_addr(CSRs.mbadaddr)) { reg_mbadaddr := wdata(vaddrBitsExtended-1,0) }
|
||||
|
||||
for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter) zipWithIndex) {
|
||||
writeCounter(i + CSR.firstMHPC, c, wdata)
|
||||
if (nPerfEvents > 1)
|
||||
when (decoded_addr(i + CSR.firstHPE)) { e := wdata }
|
||||
}
|
||||
writeCounter(CSRs.mcycle, reg_cycle, wdata)
|
||||
writeCounter(CSRs.minstret, reg_instret, wdata)
|
||||
|
||||
if (usingFPU) {
|
||||
when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
|
||||
when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
|
||||
when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
|
||||
}
|
||||
if (usingDebug) {
|
||||
when (decoded_addr(CSRs.dcsr)) {
|
||||
val new_dcsr = new DCSR().fromBits(wdata)
|
||||
reg_dcsr.halt := new_dcsr.halt
|
||||
reg_dcsr.step := new_dcsr.step
|
||||
reg_dcsr.ebreakm := new_dcsr.ebreakm
|
||||
if (usingVM) reg_dcsr.ebreaks := new_dcsr.ebreaks
|
||||
if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku
|
||||
if (usingUser) reg_dcsr.prv := trimPrivilege(new_dcsr.prv)
|
||||
}
|
||||
when (decoded_addr(CSRs.dpc)) { reg_dpc := ~(~wdata | (coreInstBytes-1)) }
|
||||
when (decoded_addr(CSRs.dscratch)) { reg_dscratch := wdata }
|
||||
}
|
||||
if (usingVM) {
|
||||
when (decoded_addr(CSRs.sstatus)) {
|
||||
val new_sstatus = new MStatus().fromBits(wdata)
|
||||
reg_mstatus.sie := new_sstatus.sie
|
||||
reg_mstatus.spie := new_sstatus.spie
|
||||
reg_mstatus.spp := new_sstatus.spp
|
||||
reg_mstatus.pum := new_sstatus.pum
|
||||
reg_mstatus.fs := Fill(2, new_sstatus.fs.orR) // even without an FPU
|
||||
if (usingRoCC) reg_mstatus.xs := Fill(2, new_sstatus.xs.orR)
|
||||
}
|
||||
when (decoded_addr(CSRs.sip)) {
|
||||
val new_sip = new MIP().fromBits(wdata)
|
||||
reg_mip.ssip := new_sip.ssip
|
||||
}
|
||||
when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~reg_mideleg) | (wdata & reg_mideleg) }
|
||||
when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
|
||||
when (decoded_addr(CSRs.sptbr)) { reg_sptbr.ppn := wdata(ppnBits-1,0) }
|
||||
when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) }
|
||||
when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata >> 2 << 2 }
|
||||
when (decoded_addr(CSRs.scause)) { reg_scause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
|
||||
when (decoded_addr(CSRs.sbadaddr)) { reg_sbadaddr := wdata(vaddrBitsExtended-1,0) }
|
||||
when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata & delegable_interrupts }
|
||||
when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata & delegable_exceptions }
|
||||
when (decoded_addr(CSRs.mscounteren)) { reg_mscounteren := wdata & UInt(delegable_counters) }
|
||||
}
|
||||
if (usingUser) {
|
||||
when (decoded_addr(CSRs.mucounteren)) { reg_mucounteren := wdata & UInt(delegable_counters) }
|
||||
}
|
||||
if (nBreakpoints > 0) {
|
||||
when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }
|
||||
|
||||
val bp = reg_bp(reg_tselect)
|
||||
when (!bp.control.dmode || reg_debug) {
|
||||
when (decoded_addr(CSRs.tdata1)) {
|
||||
val newBPC = new BPControl().fromBits(wdata)
|
||||
val dMode = newBPC.dmode && reg_debug
|
||||
bp.control := newBPC
|
||||
bp.control.dmode := dMode
|
||||
bp.control.action := dMode && newBPC.action
|
||||
}
|
||||
when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
reg_mip <> io.interrupts
|
||||
reg_dcsr.debugint := io.interrupts.debug
|
||||
|
||||
if (!usingVM) {
|
||||
reg_mideleg := 0
|
||||
reg_medeleg := 0
|
||||
reg_mscounteren := 0
|
||||
}
|
||||
|
||||
if (!usingUser) {
|
||||
reg_mucounteren := 0
|
||||
}
|
||||
|
||||
reg_sptbr.asid := 0
|
||||
if (nBreakpoints <= 1) reg_tselect := 0
|
||||
if (nBreakpoints >= 1)
|
||||
reg_bp(nBreakpoints-1).control.chain := false
|
||||
for (bpc <- reg_bp map {_.control}) {
|
||||
bpc.ttype := bpc.tType
|
||||
bpc.maskmax := bpc.maskMax
|
||||
bpc.reserved := 0
|
||||
bpc.zero := 0
|
||||
bpc.h := false
|
||||
if (!usingVM) bpc.s := false
|
||||
if (!usingUser) bpc.u := false
|
||||
if (!usingVM && !usingUser) bpc.m := true
|
||||
when (reset) {
|
||||
bpc.action := false
|
||||
bpc.dmode := false
|
||||
bpc.r := false
|
||||
bpc.w := false
|
||||
bpc.x := false
|
||||
}
|
||||
}
|
||||
for (bp <- reg_bp drop nBreakpoints)
|
||||
bp := new BP().fromBits(0)
|
||||
|
||||
def legalizePrivilege(priv: UInt): UInt =
|
||||
if (usingVM) Mux(priv === PRV.H, PRV.U, priv)
|
||||
else if (usingUser) Fill(2, priv(0))
|
||||
else PRV.M
|
||||
|
||||
def trimPrivilege(priv: UInt): UInt =
|
||||
if (usingVM) priv
|
||||
else legalizePrivilege(priv)
|
||||
|
||||
def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = {
|
||||
if (xLen == 32) {
|
||||
val hi = lo + CSRs.mcycleh - CSRs.mcycle
|
||||
when (decoded_addr(lo)) { ctr := Cat(ctr(63, 32), wdata) }
|
||||
when (decoded_addr(hi)) { ctr := Cat(wdata, ctr(31, 0)) }
|
||||
} else {
|
||||
when (decoded_addr(lo)) { ctr := wdata }
|
||||
}
|
||||
}
|
||||
def formEPC(x: UInt) = ~(~x | Cat(!reg_misa('c'-'a'), UInt(1)))
|
||||
def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).reduce(_|_)
|
||||
}
|
||||
Reference in New Issue
Block a user