Heterogeneous Tiles (#550)
Fundamental new features: * Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces. * Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile. * Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile. * Defined RocketCoreParams: All the parameters that can be varied per-core. * Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes. * Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created. * Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little. * Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support. Additional changes that got rolled in along the way: * rocket: Fix critical path through BTB for I$ index bits > pgIdxBits * coreplex: tiles connected via :=* * groundtest: updated to use TileParams * tilelink: cache cork requirements are relaxed to allow more cacheless masters
This commit is contained in:
Henry Cook
GitHub
@ -4,23 +4,33 @@
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package groundtest
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import Chisel._
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import coreplex.BareTile
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import config._
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import coreplex._
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import rocket._
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import tile._
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import uncore.tilelink._
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import uncore.util.CacheName
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import uncore.tilelink2._
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import rocketchip.ExtMem
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import diplomacy._
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import scala.util.Random
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import scala.collection.mutable.ListBuffer
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import util.ParameterizedBundle
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import config._
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import scala.collection.mutable.ListBuffer
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case object BuildGroundTest extends Field[Parameters => GroundTest]
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case class GroundTestTileSettings(
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uncached: Int = 0, cached: Int = 0, ptw: Int = 0, maxXacts: Int = 1)
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case object GroundTestKey extends Field[Seq[GroundTestTileSettings]]
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case class GroundTestTileParams(
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uncached: Int = 0,
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ptw: Int = 0,
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maxXacts: Int = 1,
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dcache: Option[DCacheParams] = Some(DCacheParams())) extends TileParams {
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val icache = None
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val btb = None
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val rocc = Nil
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val core = rocket.RocketCoreParams() //TODO remove this
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val cached = if(dcache.isDefined) 1 else 0
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val dataScratchpadBytes = 0
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}
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case object GroundTestKey extends Field[Seq[GroundTestTileParams]]
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trait HasGroundTestConstants {
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val timeoutCodeBits = 4
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@ -29,61 +39,14 @@ trait HasGroundTestConstants {
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trait HasGroundTestParameters {
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implicit val p: Parameters
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val tileSettings = p(GroundTestKey)(p(TileId))
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val nUncached = tileSettings.uncached
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val nCached = tileSettings.cached
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val nPTW = tileSettings.ptw
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val tileParams = p(GroundTestKey)(p(TileId))
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val nUncached = tileParams.uncached
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val nCached = tileParams.cached
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val nPTW = tileParams.ptw
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val memStart = p(ExtMem).base
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val memStartBlock = memStart >> p(CacheBlockOffsetBits)
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}
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class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val requestors = Vec(n, new TLBPTWIO).flip
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}
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val req_arb = Module(new RRArbiter(new PTWReq, n))
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req_arb.io.in <> io.requestors.map(_.req)
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req_arb.io.out.ready := Bool(true)
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def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
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class QueueChannel extends ParameterizedBundle()(p) {
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val ppn = UInt(width = ppnBits)
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val chosen = UInt(width = log2Up(n))
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}
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val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.addr)
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val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
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val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
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val s2_valid = Reg(next = req_arb.io.out.valid)
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val s2_resp = Wire(new PTWResp)
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s2_resp.pte.ppn := s2_ppn
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s2_resp.pte.reserved_for_software := UInt(0)
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s2_resp.pte.d := Bool(true)
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s2_resp.pte.a := Bool(false)
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s2_resp.pte.g := Bool(false)
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s2_resp.pte.u := Bool(true)
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s2_resp.pte.r := Bool(true)
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s2_resp.pte.w := Bool(true)
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s2_resp.pte.x := Bool(false)
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s2_resp.pte.v := Bool(true)
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io.requestors.zipWithIndex.foreach { case (requestor, i) =>
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requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
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requestor.resp.bits := s2_resp
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requestor.status.vm := UInt("b01000")
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requestor.status.prv := UInt(PRV.S)
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requestor.status.debug := Bool(false)
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requestor.status.mprv := Bool(true)
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requestor.status.mpp := UInt(0)
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requestor.ptbr.asid := UInt(0)
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requestor.ptbr.ppn := UInt(0)
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requestor.invalidate := Bool(false)
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}
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}
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class GroundTestStatus extends Bundle with HasGroundTestConstants {
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val finished = Bool(OUTPUT)
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val timeout = Valid(UInt(width = timeoutCodeBits))
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@ -103,38 +66,33 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
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val io = new GroundTestIO
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}
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class GroundTestTile(implicit p: Parameters) extends LazyModule with HasGroundTestParameters {
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val dcacheParams = p.alterPartial {
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case CacheName => CacheName("L1D")
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}
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class GroundTestTile(implicit p: Parameters) extends LazyModule
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with HasGroundTestParameters {
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val slave = None
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val dcache = HellaCache(p(DCacheKey))(dcacheParams)
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val dcacheOpt = tileParams.dcache.map { dc => HellaCache(dc.nMSHRs == 0) }
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val ucLegacy = LazyModule(new TLLegacy)
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val cachedOut = TLOutputNode()
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val uncachedOut = TLOutputNode()
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cachedOut := dcache.node
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uncachedOut := TLHintHandler()(ucLegacy.node)
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val masterNodes = List(cachedOut, uncachedOut)
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val masterNode = TLOutputNode()
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dcacheOpt.foreach { masterNode := _.node }
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masterNode := TLHintHandler()(ucLegacy.node)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val cached = cachedOut.bundleOut
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val uncached = uncachedOut.bundleOut
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val out = masterNode.bundleOut
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val success = Bool(OUTPUT)
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}
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val test = p(BuildGroundTest)(dcacheParams)
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val test = p(BuildGroundTest)(p)
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val ptwPorts = ListBuffer.empty ++= test.io.ptw
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val uncachedArbPorts = ListBuffer.empty ++= test.io.mem
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if (nCached > 0) {
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val dcacheArb = Module(new HellaCacheArbiter(nCached)(dcacheParams))
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dcacheOpt foreach { dcache =>
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val dcacheArb = Module(new HellaCacheArbiter(nCached))
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dcacheArb.io.requestor.zip(test.io.cache).foreach {
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case (requestor, cache) =>
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val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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val dcacheIF = Module(new SimpleHellaCacheIF())
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dcacheIF.io.requestor <> cache
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requestor <> dcacheIF.io.cache
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}
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@ -147,7 +105,7 @@ class GroundTestTile(implicit p: Parameters) extends LazyModule with HasGroundTe
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}
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if (ptwPorts.size > 0) {
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val ptw = Module(new DummyPTW(ptwPorts.size)(dcacheParams))
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val ptw = Module(new DummyPTW(ptwPorts.size))
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ptw.io.requestors <> ptwPorts
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}
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