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Heterogeneous Tiles (#550)

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Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
This commit is contained in:
Henry Cook
2017-02-09 13:59:09 -08:00
committed by GitHub
parent f9acd4988c
commit e8c8d2af71
57 changed files with 1084 additions and 1933 deletions
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6
src/main/scala/groundtest/CacheFillTest.scala
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@ -4,6 +4,7 @@
package groundtest
import Chisel._
import coreplex.CacheBlockBytes
import uncore.tilelink._
import uncore.constants._
import uncore.util._
@ -12,8 +13,9 @@ import config._
class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
with HasTileLinkParameters {
val l2Config = p(CacheName("L2"))
val capacityKb = l2Config.nSets * l2Config.nWays * l2Config.rowBits / (1024*8)
//val l2Config = p(CacheName("L2"))
//val capacityKb = l2Config.nSets * l2Config.nWays * l2Config.rowBits / (1024*8)
val capacityKb = 1024 // TODO
val nblocks = capacityKb * 1024 / p(CacheBlockBytes)
val s_start :: s_prefetch :: s_retrieve :: s_finished :: Nil = Enum(Bits(), 4)
val state = Reg(init = s_start)

80
src/main/scala/groundtest/Configs.scala
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@ -11,6 +11,7 @@ import uncore.coherence._
import uncore.agents._
import uncore.util._
import uncore.devices.NTiles
import tile.TileKey
import junctions._
import config._
import coreplex._
@ -18,10 +19,10 @@ import rocketchip._
/** Actual testing target Configs */
class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
class GroundTestConfig extends Config(new WithGroundTestTiles ++ new BaseConfig)
class ComparatorConfig extends Config(
new WithComparator ++ new GroundTestConfig)
new WithComparator(1) ++ new GroundTestConfig)
class ComparatorL2Config extends Config(
new WithAtomics ++ new WithPrefetches ++
new WithL2Cache ++ new ComparatorConfig)
@ -30,31 +31,32 @@ class ComparatorBufferlessConfig extends Config(
class ComparatorStatelessConfig extends Config(
new WithStatelessBridge ++ new ComparatorConfig)
class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
class MemtestConfig extends Config(new WithMemtest(1) ++ new GroundTestConfig)
class MemtestL2Config extends Config(
new WithL2Cache ++ new MemtestConfig)
class MemtestBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new MemtestConfig)
class MemtestStatelessConfig extends Config(
new WithNGenerators(0, 1) ++ new WithStatelessBridge ++ new MemtestConfig)
new WithStatelessBridge ++ new MemtestConfig)
// Test ALL the things
class FancyMemtestConfig extends Config(
new WithNGenerators(1, 2) ++ new WithNCores(2) ++ new WithMemtest ++
new WithMemtest(2) ++
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
new WithL2Cache ++ new GroundTestConfig)
class CacheFillTestConfig extends Config(
new WithNL2Ways(4) ++ new WithL2Capacity(4) ++ new WithCacheFillTest ++ new WithL2Cache ++ new GroundTestConfig)
new WithNL2Ways(4) ++ new WithL2Capacity(4) ++
new WithCacheFillTest(1) ++ new WithL2Cache ++ new GroundTestConfig)
class BroadcastRegressionTestConfig extends Config(
new WithBroadcastRegressionTest ++ new GroundTestConfig)
new WithBroadcastRegressionTest(1) ++ new GroundTestConfig)
class BufferlessRegressionTestConfig extends Config(
new WithBufferlessBroadcastHub ++ new BroadcastRegressionTestConfig)
class CacheRegressionTestConfig extends Config(
new WithCacheRegressionTest ++ new WithL2Cache ++ new GroundTestConfig)
new WithCacheRegressionTest(1) ++ new WithL2Cache ++ new GroundTestConfig)
class TraceGenConfig extends Config(
new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig)
new WithTraceGen(2) ++ new GroundTestConfig)
class TraceGenBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new TraceGenConfig)
class TraceGenL2Config extends Config(
@ -72,15 +74,15 @@ class Edge32BitMemtestConfig extends Config(
new WithEdgeDataBits(32) ++ new MemtestConfig)
/* Composable Configs to set individual parameters */
class WithGroundTest extends Config((site, here, up) => {
case FPUKey => None
case UseAtomics => false
case UseCompressed => false
class WithGroundTestTiles extends Config((site, here, up) => {
case TileKey => site(GroundTestKey).head
case NTiles => site(GroundTestKey).size
})
class WithComparator extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(site(NTiles)) {
GroundTestTileSettings(uncached = 2)
class WithComparator(n: Int) extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(n) {
GroundTestTileParams(uncached = 2, dcache = None)
}
case BuildGroundTest =>
(p: Parameters) => Module(new ComparatorCore()(p))
@ -88,23 +90,21 @@ class WithComparator extends Config((site, here, up) => {
targets = Seq(site(ExtMem).base, testRamAddr),
width = 8,
operations = 1000,
atomics = site(UseAtomics),
atomics = false,
prefetches = false)
case FPUConfig => None
case UseAtomics => false
})
class WithAtomics extends Config((site, here, up) => {
case UseAtomics => true
case ComparatorKey => up(ComparatorKey, site).copy(atomics = true)
})
class WithPrefetches extends Config((site, here, up) => {
case ComparatorKey => up(ComparatorKey, site).copy(prefetches = true)
})
class WithMemtest extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(site(NTiles)) {
GroundTestTileSettings(1, 1)
class WithMemtest(n: Int) extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(n) {
GroundTestTileParams(uncached = 1)
}
case GeneratorKey => TrafficGeneratorParameters(
maxRequests = 128,
@ -113,23 +113,17 @@ class WithMemtest extends Config((site, here, up) => {
(p: Parameters) => Module(new GeneratorTest()(p))
})
class WithNGenerators(nUncached: Int, nCached: Int) extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(site(NTiles)) {
GroundTestTileSettings(nUncached, nCached)
}
})
class WithCacheFillTest extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(site(NTiles)) {
GroundTestTileSettings(uncached = 1)
class WithCacheFillTest(n: Int) extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(n) {
GroundTestTileParams(uncached = 1, dcache = None)
}
case BuildGroundTest =>
(p: Parameters) => Module(new CacheFillTest()(p))
})
class WithBroadcastRegressionTest extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(site(NTiles)) {
GroundTestTileSettings(1, 1, maxXacts = 3)
class WithBroadcastRegressionTest(n: Int) extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(n) {
GroundTestTileParams(uncached = 1, maxXacts = 3)
}
case BuildGroundTest =>
(p: Parameters) => Module(new RegressionTest()(p))
@ -137,9 +131,9 @@ class WithBroadcastRegressionTest extends Config((site, here, up) => {
(p: Parameters) => RegressionTests.broadcastRegressions(p)
})
class WithCacheRegressionTest extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(site(NTiles)) {
GroundTestTileSettings(1, 1, maxXacts = 5)
class WithCacheRegressionTest(n: Int) extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(n) {
GroundTestTileParams(uncached = 1, maxXacts = 5)
}
case BuildGroundTest =>
(p: Parameters) => Module(new RegressionTest()(p))
@ -147,9 +141,9 @@ class WithCacheRegressionTest extends Config((site, here, up) => {
(p: Parameters) => RegressionTests.cacheRegressions(p)
})
class WithTraceGen extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(site(NTiles)) {
GroundTestTileSettings(uncached = 0, cached = 1)
class WithTraceGen(n: Int) extends Config((site, here, up) => {
case GroundTestKey => Seq.fill(n) {
GroundTestTileParams(dcache = Some(DCacheParams(nSets = 16, nWays = 1)))
}
case BuildGroundTest =>
(p: Parameters) => Module(new GroundTestTraceGenerator()(p))
@ -160,11 +154,9 @@ class WithTraceGen extends Config((site, here, up) => {
val nSets = 2
val nWays = 1
val blockOffset = site(CacheBlockOffsetBits)
val nBeats = site(TLKey("L1toL2")).dataBeats
val nBeats = site(CacheBlockBytes)/site(L1toL2Config).beatBytes
List.tabulate(4 * nWays) { i =>
Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
}.flatten
}
case UseAtomics => true
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 16, nWays = 1)
})

13
src/main/scala/groundtest/Coreplex.scala
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@ -7,6 +7,7 @@ import config._
import diplomacy._
import coreplex._
import rocket._
import tile._
import uncore.agents._
import uncore.coherence._
import uncore.devices._
@ -31,9 +32,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
nManagers = site(BankedL2Config).nBanks + 1,
nCachingClients = 1,
nCachelessClients = 1,
maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
site(GroundTestKey).map(_.maxXacts))
.reduce(max(_, _)),
maxClientXacts = site(GroundTestKey).map(_.maxXacts).reduce(max(_, _)),
maxClientsPerPort = site(GroundTestKey).map(_.uncached).sum,
maxManagerXacts = 8,
dataBeats = (8 * site(CacheBlockBytes)) / site(XLen),
@ -41,10 +40,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
}}))
}
tiles.foreach { lm =>
l1tol2.node := lm.cachedOut
l1tol2.node := lm.uncachedOut
}
tiles.foreach { l1tol2.node :=* _.masterNode }
val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))
cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
@ -52,8 +48,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))
}
class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
{
class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) {
val success = Bool(OUTPUT)
}

57
src/main/scala/groundtest/DummyPTW.scala Normal file
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@ -0,0 +1,57 @@
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package groundtest
import Chisel._
import config._
import rocket._
import tile._
import util.ParameterizedBundle
class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val requestors = Vec(n, new TLBPTWIO).flip
}
val req_arb = Module(new RRArbiter(new PTWReq, n))
req_arb.io.in <> io.requestors.map(_.req)
req_arb.io.out.ready := Bool(true)
def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
class QueueChannel extends ParameterizedBundle()(p) {
val ppn = UInt(width = ppnBits)
val chosen = UInt(width = log2Up(n))
}
val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.addr)
val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
val s2_valid = Reg(next = req_arb.io.out.valid)
val s2_resp = Wire(new PTWResp)
s2_resp.pte.ppn := s2_ppn
s2_resp.pte.reserved_for_software := UInt(0)
s2_resp.pte.d := Bool(true)
s2_resp.pte.a := Bool(false)
s2_resp.pte.g := Bool(false)
s2_resp.pte.u := Bool(true)
s2_resp.pte.r := Bool(true)
s2_resp.pte.w := Bool(true)
s2_resp.pte.x := Bool(false)
s2_resp.pte.v := Bool(true)
io.requestors.zipWithIndex.foreach { case (requestor, i) =>
requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
requestor.resp.bits := s2_resp
requestor.status.vm := UInt("b01000")
requestor.status.prv := UInt(PRV.S)
requestor.status.debug := Bool(false)
requestor.status.mprv := Bool(true)
requestor.status.mpp := UInt(0)
requestor.ptbr.asid := UInt(0)
requestor.ptbr.ppn := UInt(0)
requestor.invalidate := Bool(false)
}
}

31
src/main/scala/groundtest/Regression.scala
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@ -103,14 +103,13 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
* acknowledge both of them when the first one finished.
* This caused the state to go funky since the next time around it would
* start the put in the middle */
class PutBlockMergeRegression(implicit p: Parameters)
class PutBlockMergeRegression(nSets: Int)(implicit p: Parameters)
extends Regression()(p) with HasTileLinkParameters {
val s_idle :: s_put :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
val state = Reg(init = s_idle)
disableCache()
val nSets = p(CacheName("L2")).nSets
val addr_blocks = Vec(Seq(0, 0, nSets).map(num => UInt(num + memStartBlock)))
val nSteps = addr_blocks.size
val (acq_beat, acq_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
@ -391,12 +390,9 @@ class PrefetchHitRegression(implicit p: Parameters) extends Regression()(p) {
* set. This assumes that there is only a single cache bank. If we want to
* test multibank configurations, we'll have to think of some other way to
* determine which banks are conflicting */
class WritebackRegression(implicit p: Parameters) extends Regression()(p) {
class WritebackRegression(nSets: Int, nWays: Int)(implicit p: Parameters) extends Regression()(p) {
disableCache()
val nSets = p(CacheName("L2")).nSets
val nWays = p(CacheName("L2")).nWays
val addr_blocks = Vec.tabulate(nWays + 1) { i => UInt(memStartBlock + i * nSets) }
val data = Vec.tabulate(nWays + 1) { i => UInt((i + 1) * 1423) }
@ -443,11 +439,9 @@ class WritebackRegression(implicit p: Parameters) extends Regression()(p) {
io.errored := data_mismatch
}
class ReleaseRegression(implicit p: Parameters) extends Regression()(p) {
class ReleaseRegression(nSets: Int, nWays: Int)(implicit p: Parameters) extends Regression()(p) {
disableMem()
val nSets = p(CacheName("L1D")).nSets
val nWays = p(CacheName("L1D")).nWays
val blockOffset = p(CacheBlockOffsetBits)
val startBlock = memStartBlock + 10
@ -530,12 +524,9 @@ class PutBeforePutBlockRegression(implicit p: Parameters) extends Regression()(p
* Make sure that multiple gets to the same line and beat are merged
* correctly, even if it is a cache miss.
*/
class MergedGetRegression(implicit p: Parameters) extends Regression()(p) {
class MergedGetRegression(nSets: Int, nWays: Int)(implicit p: Parameters) extends Regression()(p) {
disableCache()
val nSets = p(CacheName("L2")).nSets
val nWays = p(CacheName("L2")).nWays
val (s_idle :: s_put :: s_get :: s_done :: Nil) = Enum(Bits(), 4)
val state = Reg(init = s_idle)
@ -697,23 +688,27 @@ class PutAfterReleaseRegression(implicit p: Parameters) extends Regression()(p)
}
object RegressionTests {
val l1sets = 16 // TODO
val l1ways = 1 // TODO
val l2sets = 32 // TODO
val l2ways = 2 // TODO
def cacheRegressions(implicit p: Parameters) = Seq(
Module(new PutBlockMergeRegression),
Module(new PutBlockMergeRegression(l2sets)),
Module(new NoAllocPutHitRegression),
Module(new RepeatedNoAllocPutRegression),
Module(new WriteMaskedPutBlockRegression),
Module(new PrefetchHitRegression),
Module(new WritebackRegression),
Module(new WritebackRegression(l2sets, l2ways)),
Module(new PutBeforePutBlockRegression),
Module(new MixedAllocPutRegression),
Module(new ReleaseRegression),
Module(new MergedGetRegression),
Module(new ReleaseRegression(l1sets, l1ways)),
Module(new MergedGetRegression(l2sets, l2ways)),
Module(new MergedPutRegression))
def broadcastRegressions(implicit p: Parameters) = Seq(
Module(new IOGetAfterPutBlockRegression),
Module(new WriteMaskedPutBlockRegression),
Module(new PutBeforePutBlockRegression),
Module(new ReleaseRegression),
Module(new ReleaseRegression(l1sets, l1ways)),
Module(new PutAfterReleaseRegression))
}

110
src/main/scala/groundtest/Tile.scala
View File

@ -4,23 +4,33 @@
package groundtest
import Chisel._
import coreplex.BareTile
import config._
import coreplex._
import rocket._
import tile._
import uncore.tilelink._
import uncore.util.CacheName
import uncore.tilelink2._
import rocketchip.ExtMem
import diplomacy._
import scala.util.Random
import scala.collection.mutable.ListBuffer
import util.ParameterizedBundle
import config._
import scala.collection.mutable.ListBuffer
case object BuildGroundTest extends Field[Parameters => GroundTest]
case class GroundTestTileSettings(
uncached: Int = 0, cached: Int = 0, ptw: Int = 0, maxXacts: Int = 1)
case object GroundTestKey extends Field[Seq[GroundTestTileSettings]]
case class GroundTestTileParams(
uncached: Int = 0,
ptw: Int = 0,
maxXacts: Int = 1,
dcache: Option[DCacheParams] = Some(DCacheParams())) extends TileParams {
val icache = None
val btb = None
val rocc = Nil
val core = rocket.RocketCoreParams() //TODO remove this
val cached = if(dcache.isDefined) 1 else 0
val dataScratchpadBytes = 0
}
case object GroundTestKey extends Field[Seq[GroundTestTileParams]]
trait HasGroundTestConstants {
val timeoutCodeBits = 4
@ -29,61 +39,14 @@ trait HasGroundTestConstants {
trait HasGroundTestParameters {
implicit val p: Parameters
val tileSettings = p(GroundTestKey)(p(TileId))
val nUncached = tileSettings.uncached
val nCached = tileSettings.cached
val nPTW = tileSettings.ptw
val tileParams = p(GroundTestKey)(p(TileId))
val nUncached = tileParams.uncached
val nCached = tileParams.cached
val nPTW = tileParams.ptw
val memStart = p(ExtMem).base
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
}
class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val requestors = Vec(n, new TLBPTWIO).flip
}
val req_arb = Module(new RRArbiter(new PTWReq, n))
req_arb.io.in <> io.requestors.map(_.req)
req_arb.io.out.ready := Bool(true)
def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
class QueueChannel extends ParameterizedBundle()(p) {
val ppn = UInt(width = ppnBits)
val chosen = UInt(width = log2Up(n))
}
val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.addr)
val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
val s2_valid = Reg(next = req_arb.io.out.valid)
val s2_resp = Wire(new PTWResp)
s2_resp.pte.ppn := s2_ppn
s2_resp.pte.reserved_for_software := UInt(0)
s2_resp.pte.d := Bool(true)
s2_resp.pte.a := Bool(false)
s2_resp.pte.g := Bool(false)
s2_resp.pte.u := Bool(true)
s2_resp.pte.r := Bool(true)
s2_resp.pte.w := Bool(true)
s2_resp.pte.x := Bool(false)
s2_resp.pte.v := Bool(true)
io.requestors.zipWithIndex.foreach { case (requestor, i) =>
requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
requestor.resp.bits := s2_resp
requestor.status.vm := UInt("b01000")
requestor.status.prv := UInt(PRV.S)
requestor.status.debug := Bool(false)
requestor.status.mprv := Bool(true)
requestor.status.mpp := UInt(0)
requestor.ptbr.asid := UInt(0)
requestor.ptbr.ppn := UInt(0)
requestor.invalidate := Bool(false)
}
}
class GroundTestStatus extends Bundle with HasGroundTestConstants {
val finished = Bool(OUTPUT)
val timeout = Valid(UInt(width = timeoutCodeBits))
@ -103,38 +66,33 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
val io = new GroundTestIO
}
class GroundTestTile(implicit p: Parameters) extends LazyModule with HasGroundTestParameters {
val dcacheParams = p.alterPartial {
case CacheName => CacheName("L1D")
}
class GroundTestTile(implicit p: Parameters) extends LazyModule
with HasGroundTestParameters {
val slave = None
val dcache = HellaCache(p(DCacheKey))(dcacheParams)
val dcacheOpt = tileParams.dcache.map { dc => HellaCache(dc.nMSHRs == 0) }
val ucLegacy = LazyModule(new TLLegacy)
val cachedOut = TLOutputNode()
val uncachedOut = TLOutputNode()
cachedOut := dcache.node
uncachedOut := TLHintHandler()(ucLegacy.node)
val masterNodes = List(cachedOut, uncachedOut)
val masterNode = TLOutputNode()
dcacheOpt.foreach { masterNode := _.node }
masterNode := TLHintHandler()(ucLegacy.node)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val cached = cachedOut.bundleOut
val uncached = uncachedOut.bundleOut
val out = masterNode.bundleOut
val success = Bool(OUTPUT)
}
val test = p(BuildGroundTest)(dcacheParams)
val test = p(BuildGroundTest)(p)
val ptwPorts = ListBuffer.empty ++= test.io.ptw
val uncachedArbPorts = ListBuffer.empty ++= test.io.mem
if (nCached > 0) {
val dcacheArb = Module(new HellaCacheArbiter(nCached)(dcacheParams))
dcacheOpt foreach { dcache =>
val dcacheArb = Module(new HellaCacheArbiter(nCached))
dcacheArb.io.requestor.zip(test.io.cache).foreach {
case (requestor, cache) =>
val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
val dcacheIF = Module(new SimpleHellaCacheIF())
dcacheIF.io.requestor <> cache
requestor <> dcacheIF.io.cache
}
@ -147,7 +105,7 @@ class GroundTestTile(implicit p: Parameters) extends LazyModule with HasGroundTe
}
if (ptwPorts.size > 0) {
val ptw = Module(new DummyPTW(ptwPorts.size)(dcacheParams))
val ptw = Module(new DummyPTW(ptwPorts.size))
ptw.io.requestors <> ptwPorts
}

3
src/main/scala/groundtest/TraceGen.scala
View File

@ -24,6 +24,7 @@ import uncore.tilelink._
import uncore.constants._
import uncore.devices.NTiles
import rocket._
import tile._
import util.{Timer, DynamicTimer}
import scala.util.Random
import config._
@ -179,7 +180,7 @@ class TagMan(val logNumTags : Int) extends Module {
// ===============
class TraceGenerator(id: Int)
(implicit p: Parameters) extends L1HellaCacheModule()(p)
(implicit val p: Parameters) extends Module
with HasTraceGenParams
with HasGroundTestParameters {
val io = new Bundle {

2
src/main/scala/groundtest/TrafficGenerator.scala
View File

@ -129,7 +129,7 @@ class UncachedTileLinkGenerator(id: Int)
}
class HellaCacheGenerator(id: Int)
(implicit p: Parameters) extends L1HellaCacheModule()(p) with HasTrafficGeneratorParameters {
(implicit val p: Parameters) extends Module with HasTrafficGeneratorParameters {
val io = new Bundle {
val mem = new HellaCacheIO
val status = new GroundTestStatus