Heterogeneous Tiles (#550)

Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters

src/main/scala/coreplex/Configs.scala

@@ -7,6 +7,7 @@ import Chisel._
 import config._
 import diplomacy._
 import rocket._
+import tile._
 import uncore.converters._
 import uncore.devices._
 import uncore.tilelink2._
@@ -14,71 +15,42 @@ import uncore.util._
 import util._
 
 class BaseCoreplexConfig extends Config ((site, here, up) => {
-  //Memory Parameters
   case PAddrBits => 32
   case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
   case ASIdBits => 7
+  case XLen => 64 // Applies to all cores
+  case BuildCore => (p: Parameters) => new Rocket()(p)
   case RocketCrossing => Synchronous
-  //Params used by all caches
-  case CacheName("L1I") => CacheConfig(
-    nSets         = 64,
-    nWays         = 4,
-    rowBits       = site(L1toL2Config).beatBytes*8,
-    nTLBEntries   = 8,
-    cacheIdBits   = 0,
-    splitMetadata = false)
-  case CacheName("L1D") => CacheConfig(
-    nSets         = 64,
-    nWays         = 4,
-    rowBits       = site(L1toL2Config).beatBytes*8,
-    nTLBEntries   = 8,
-    cacheIdBits   = 0,
-    splitMetadata = false)
-  case ECCCode => None
-  case Replacer => () => new RandomReplacement(site(site(CacheName)).nWays)
-  //L1InstCache
-  case BtbKey => BtbParameters()
-  //L1DataCache
-  case DCacheKey => DCacheConfig(nMSHRs = 2)
-  case DataScratchpadSize => 0
-  //Tile Constants
-  case BuildRoCC => Nil
-  //Rocket Core Constants
-  case CoreInstBits => if (site(UseCompressed)) 16 else 32
-  case FetchWidth => if (site(UseCompressed)) 2 else 1
-  case RetireWidth => 1
-  case UseVM => true
-  case UseUser => false
-  case UseDebug => true
-  case NBreakpoints => 1
-  case NPerfCounters => 0
-  case NPerfEvents => 0
-  case FastLoadWord => true
-  case FastLoadByte => false
-  case FastJAL => false
-  case XLen => 64
-  case FPUKey => Some(FPUConfig())
-  case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true))
-  case UseAtomics => true
-  case UseCompressed => true
+  case RocketTilesKey =>  Nil
   case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
-  case NCustomMRWCSRs => 0
-  case MtvecInit => Some(BigInt(0))
-  case MtvecWritable => true
-  //Uncore Paramters
+  case NTiles => site(RocketTilesKey).size
   case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
   case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth
   case BootROMFile => "./bootrom/bootrom.img"
-  case NTiles => site(RocketConfigs).size
-  case RocketConfigs => List(RocketConfig(site(XLen)))
-  case BuildCore => (c: RocketConfig, p: Parameters) => new Rocket(c)(p)
   case BroadcastConfig => BroadcastConfig()
   case BankedL2Config => BankedL2Config()
   case CacheBlockBytes => 64
 })
 
-class WithNCores(n: Int) extends Config((site, here, up) => {
-  case RocketConfigs => List.fill(n){ RocketConfig(site(XLen)) }
+class WithNBigCores(n: Int) extends Config((site, here, up) => {
+  case RocketTilesKey => {
+    val big = RocketTileParams(
+      core   = RocketCoreParams(mulDiv = Some(MulDivParams(mulUnroll = 8, mulEarlyOut = true, divEarlyOut = true))),
+      dcache = Some(DCacheParams(rowBits = site(L1toL2Config).beatBytes*8, nMSHRs  = 2)),
+      icache = Some(ICacheParams(rowBits = site(L1toL2Config).beatBytes*8)))
+    List.fill(n)(big) ++ up(RocketTilesKey, site)
+  }
+})
+
+class WithNSmallCores(n: Int) extends Config((site, here, up) => {
+  case RocketTilesKey => {
+    val small = RocketTileParams(
+      core = RocketCoreParams(useVM = false, fpu = None),
+      btb = None,
+      dcache = Some(DCacheParams(rowBits = site(L1toL2Config).beatBytes*8, nSets = 64, nWays = 1, nTLBEntries = 4, nMSHRs = 0)),
+      icache = Some(ICacheParams(rowBits = site(L1toL2Config).beatBytes*8, nSets = 64, nWays = 1, nTLBEntries = 4)))
+    List.fill(n)(small) ++ up(RocketTilesKey, site)
+  }
 })
 
 class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => {
@@ -89,43 +61,50 @@ class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => {
   case BroadcastConfig => up(BroadcastConfig, site).copy(nTrackers = n)
 })
 
-// This is the number of sets **per way**
+// This is the number of icache sets for all Rocket tiles
 class WithL1ICacheSets(sets: Int) extends Config((site, here, up) => {
-  case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = sets)
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(icache = r.icache.map(_.copy(nSets = sets))) }
 })
 
-// This is the number of sets **per way**
+// This is the number of icache sets for all Rocket tiles
 class WithL1DCacheSets(sets: Int) extends Config((site, here, up) => {
-  case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = sets)
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(dcache = r.dcache.map(_.copy(nSets = sets))) }
 })
 
 class WithL1ICacheWays(ways: Int) extends Config((site, here, up) => {
-  case CacheName("L1I") => up(CacheName("L1I"), site).copy(nWays = ways)
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(icache = r.icache.map(_.copy(nWays = ways)))
+  }
 })
 
 class WithL1DCacheWays(ways: Int) extends Config((site, here, up) => {
-  case CacheName("L1D") => up(CacheName("L1D"), site).copy(nWays = ways)
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(dcache = r.dcache.map(_.copy(nWays = ways)))
+  }
 })
 
 class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
   case CacheBlockBytes => linesize
 })
 
-class WithDataScratchpad(n: Int) extends Config((site, here, up) => {
-  case DataScratchpadSize => n
-  case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = n / site(CacheBlockBytes))
+/** Warning: applies only to the most recently added tile.
+  * TODO: For now, there can only be a single scratchpad in the design
+  *       because its address is hardcoded.
+  */
+class WithDataScratchpad(size: Int) extends Config((site, here, up) => {
+  case RocketTilesKey => {
+    val prev = up(RocketTilesKey, site)
+    prev.head.copy(
+      dcache = prev.head.dcache.map(_.copy(nSets = size / site(CacheBlockBytes))),
+      dataScratchpadBytes = size) +: prev.tail
+  }
 })
 
-// TODO: re-add L2
-class WithL2Cache extends Config((site, here, up) => {
-  case CacheName("L2") => CacheConfig(
-    nSets         = 1024,
-    nWays         = 1,
-    rowBits       = site(L1toL2Config).beatBytes*8,
-    nTLBEntries   = 0,
-    cacheIdBits   = 1,
-    splitMetadata = false)
-})
+class WithL2Cache extends Config(Parameters.empty) // TODO: re-add L2
+class WithL2Capacity(size_kb: Int) extends Config(Parameters.empty) // TODO: re-add L2
+class WithNL2Ways(n: Int) extends Config(Parameters.empty) // TODO: re-add L2
 
 class WithBufferlessBroadcastHub extends Config((site, here, up) => {
   case BroadcastConfig => up(BroadcastConfig, site).copy(bufferless = true)
@@ -151,44 +130,39 @@ class WithStatelessBridge extends Config((site, here, up) => {
     ww.node :*= cork.node
     (cork.node, ww.node)
   })
-  case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
-})
-
-class WithL2Capacity(size_kb: Int) extends Config(Parameters.empty) // TODO
-
-class WithNL2Ways(n: Int) extends Config((site, here, up) => {
-  case CacheName("L2") => up(CacheName("L2"), site).copy(nWays = n)
 })
 
 class WithRV32 extends Config((site, here, up) => {
   case XLen => 32
-  case FPUKey => Some(FPUConfig(divSqrt = false))
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(core = r.core.copy(
+      mulDiv = Some(MulDivParams(mulUnroll = 8)),
+      fpu = r.core.fpu.map(_.copy(divSqrt = false))))
+  }
 })
 
 class WithBlockingL1 extends Config((site, here, up) => {
-  case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(dcache = r.dcache.map(_.copy(nMSHRs = 0)))
+  }
 })
 
-class WithSmallCores extends Config((site, here, up) => {
-  case MulDivKey => Some(MulDivConfig())
-  case FPUKey => None
-  case UseVM => false
-  case BtbKey => BtbParameters(nEntries = 0)
-  case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
-  case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
-  case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
+class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(core = r.core.copy(nBreakpoints = hwbp))
+  }
 })
 
 class WithRoccExample extends Config((site, here, up) => {
   case BuildRoCC => Seq(
-    RoccParameters(
+    RoCCParams(
       opcodes = OpcodeSet.custom0,
       generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
-    RoccParameters(
+    RoCCParams(
       opcodes = OpcodeSet.custom1,
       generator = (p: Parameters) => Module(new TranslatorExample()(p)),
       nPTWPorts = 1),
-    RoccParameters(
+    RoCCParams(
       opcodes = OpcodeSet.custom2,
       generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
 
@@ -196,23 +170,34 @@ class WithRoccExample extends Config((site, here, up) => {
 })
 
 class WithDefaultBtb extends Config((site, here, up) => {
-  case BtbKey => BtbParameters()
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(btb = Some(BTBParams()))
+  }
 })
 
 class WithFastMulDiv extends Config((site, here, up) => {
-  case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true))
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(core = r.core.copy(mulDiv = Some(
+      MulDivParams(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true)
+  )))}
 })
 
 class WithoutMulDiv extends Config((site, here, up) => {
-  case MulDivKey => None
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(core = r.core.copy(mulDiv = None))
+  }
 })
 
 class WithoutFPU extends Config((site, here, up) => {
-  case FPUKey => None
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(core = r.core.copy(fpu = None))
+  }
 })
 
 class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
-  case FPUKey => Some(FPUConfig(divSqrt = false))
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(core = r.core.copy(fpu = r.core.fpu.map(_.copy(divSqrt = false))))
+  }
 })
 
 class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {