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Heterogeneous Tiles (#550)

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Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
This commit is contained in:
Henry Cook
2017-02-09 13:59:09 -08:00
committed by GitHub
parent f9acd4988c
commit e8c8d2af71
57 changed files with 1084 additions and 1933 deletions
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12
src/main/scala/coreplex/BaseCoreplex.scala
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@ -5,9 +5,9 @@ package coreplex
import Chisel._
import config._
import diplomacy._
import rocket.{TileInterrupts, XLen}
import tile.XLen
import tile.TileInterrupts
import uncore.tilelink2._
import uncore.util._
import util._
/** Widths of various points in the SoC */
@ -15,6 +15,9 @@ case class TLBusConfig(beatBytes: Int)
case object CBusConfig extends Field[TLBusConfig]
case object L1toL2Config extends Field[TLBusConfig]
// These parameters apply to all caches, for now
case object CacheBlockBytes extends Field[Int]
/** L2 Broadcast Hub configuration */
case class BroadcastConfig(
nTrackers: Int = 4,
@ -42,10 +45,11 @@ case object BootROMFile extends Field[String]
trait HasCoreplexParameters {
implicit val p: Parameters
lazy val tilesParams = p(RocketTilesKey)
lazy val cbusConfig = p(CBusConfig)
lazy val l1tol2Config = p(L1toL2Config)
lazy val nTiles = p(uncore.devices.NTiles)
lazy val hasSupervisor = p(rocket.UseVM)
lazy val nTiles = tilesParams.size
lazy val hasSupervisor = tilesParams.exists(_.core.useVM) // TODO ask andrew about this
lazy val l2Config = p(BankedL2Config)
}

56
src/main/scala/coreplex/BaseTile.scala
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@ -1,56 +0,0 @@
// See LICENSE.SiFive for license details.
package coreplex
import Chisel._
import config._
import diplomacy._
import rocket.{TileInterrupts, XLen}
import uncore.tilelink2._
import util.GenericParameterizedBundle
abstract class BareTile(implicit p: Parameters) extends LazyModule
abstract class BareTileBundle[+L <: BareTile](_outer: L) extends GenericParameterizedBundle(_outer) {
val outer = _outer
implicit val p = outer.p
}
abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
val outer = _outer
val io = _io ()
}
// Uses a tile-internal crossbar to provide a single TileLink master port
trait TileNetwork {
implicit val p: Parameters
val module: TileNetworkModule
val l1backend = LazyModule(new TLXbar)
val masterNodes = List(TLOutputNode())
masterNodes.head := l1backend.node
}
trait TileNetworkBundle {
val outer: TileNetwork
val master = outer.masterNodes.head.bundleOut
}
trait TileNetworkModule {
val outer: TileNetwork
val io: TileNetworkBundle
}
abstract class BaseTile(implicit p: Parameters) extends BareTile
with TileNetwork {
override lazy val module = new BaseTileModule(this, () => new BaseTileBundle(this))
}
class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
with TileNetworkBundle {
val hartid = UInt(INPUT, p(XLen))
val interrupts = new TileInterrupts()(p).asInput
val resetVector = UInt(INPUT, p(XLen))
}
class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
with TileNetworkModule

177
src/main/scala/coreplex/Configs.scala
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@ -7,6 +7,7 @@ import Chisel._
import config._
import diplomacy._
import rocket._
import tile._
import uncore.converters._
import uncore.devices._
import uncore.tilelink2._
@ -14,71 +15,42 @@ import uncore.util._
import util._
class BaseCoreplexConfig extends Config ((site, here, up) => {
//Memory Parameters
case PAddrBits => 32
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
case ASIdBits => 7
case XLen => 64 // Applies to all cores
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketCrossing => Synchronous
//Params used by all caches
case CacheName("L1I") => CacheConfig(
nSets = 64,
nWays = 4,
rowBits = site(L1toL2Config).beatBytes*8,
nTLBEntries = 8,
cacheIdBits = 0,
splitMetadata = false)
case CacheName("L1D") => CacheConfig(
nSets = 64,
nWays = 4,
rowBits = site(L1toL2Config).beatBytes*8,
nTLBEntries = 8,
cacheIdBits = 0,
splitMetadata = false)
case ECCCode => None
case Replacer => () => new RandomReplacement(site(site(CacheName)).nWays)
//L1InstCache
case BtbKey => BtbParameters()
//L1DataCache
case DCacheKey => DCacheConfig(nMSHRs = 2)
case DataScratchpadSize => 0
//Tile Constants
case BuildRoCC => Nil
//Rocket Core Constants
case CoreInstBits => if (site(UseCompressed)) 16 else 32
case FetchWidth => if (site(UseCompressed)) 2 else 1
case RetireWidth => 1
case UseVM => true
case UseUser => false
case UseDebug => true
case NBreakpoints => 1
case NPerfCounters => 0
case NPerfEvents => 0
case FastLoadWord => true
case FastLoadByte => false
case FastJAL => false
case XLen => 64
case FPUKey => Some(FPUConfig())
case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true))
case UseAtomics => true
case UseCompressed => true
case RocketTilesKey => Nil
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
case NCustomMRWCSRs => 0
case MtvecInit => Some(BigInt(0))
case MtvecWritable => true
//Uncore Paramters
case NTiles => site(RocketTilesKey).size
case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth
case BootROMFile => "./bootrom/bootrom.img"
case NTiles => site(RocketConfigs).size
case RocketConfigs => List(RocketConfig(site(XLen)))
case BuildCore => (c: RocketConfig, p: Parameters) => new Rocket(c)(p)
case BroadcastConfig => BroadcastConfig()
case BankedL2Config => BankedL2Config()
case CacheBlockBytes => 64
})
class WithNCores(n: Int) extends Config((site, here, up) => {
case RocketConfigs => List.fill(n){ RocketConfig(site(XLen)) }
class WithNBigCores(n: Int) extends Config((site, here, up) => {
case RocketTilesKey => {
val big = RocketTileParams(
core = RocketCoreParams(mulDiv = Some(MulDivParams(mulUnroll = 8, mulEarlyOut = true, divEarlyOut = true))),
dcache = Some(DCacheParams(rowBits = site(L1toL2Config).beatBytes*8, nMSHRs = 2)),
icache = Some(ICacheParams(rowBits = site(L1toL2Config).beatBytes*8)))
List.fill(n)(big) ++ up(RocketTilesKey, site)
}
})
class WithNSmallCores(n: Int) extends Config((site, here, up) => {
case RocketTilesKey => {
val small = RocketTileParams(
core = RocketCoreParams(useVM = false, fpu = None),
btb = None,
dcache = Some(DCacheParams(rowBits = site(L1toL2Config).beatBytes*8, nSets = 64, nWays = 1, nTLBEntries = 4, nMSHRs = 0)),
icache = Some(ICacheParams(rowBits = site(L1toL2Config).beatBytes*8, nSets = 64, nWays = 1, nTLBEntries = 4)))
List.fill(n)(small) ++ up(RocketTilesKey, site)
}
})
class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => {
@ -89,43 +61,50 @@ class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => {
case BroadcastConfig => up(BroadcastConfig, site).copy(nTrackers = n)
})
// This is the number of sets **per way**
// This is the number of icache sets for all Rocket tiles
class WithL1ICacheSets(sets: Int) extends Config((site, here, up) => {
case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = sets)
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(icache = r.icache.map(_.copy(nSets = sets))) }
})
// This is the number of sets **per way**
// This is the number of icache sets for all Rocket tiles
class WithL1DCacheSets(sets: Int) extends Config((site, here, up) => {
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = sets)
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(dcache = r.dcache.map(_.copy(nSets = sets))) }
})
class WithL1ICacheWays(ways: Int) extends Config((site, here, up) => {
case CacheName("L1I") => up(CacheName("L1I"), site).copy(nWays = ways)
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(icache = r.icache.map(_.copy(nWays = ways)))
}
})
class WithL1DCacheWays(ways: Int) extends Config((site, here, up) => {
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nWays = ways)
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(dcache = r.dcache.map(_.copy(nWays = ways)))
}
})
class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
case CacheBlockBytes => linesize
})
class WithDataScratchpad(n: Int) extends Config((site, here, up) => {
case DataScratchpadSize => n
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = n / site(CacheBlockBytes))
/** Warning: applies only to the most recently added tile.
* TODO: For now, there can only be a single scratchpad in the design
* because its address is hardcoded.
*/
class WithDataScratchpad(size: Int) extends Config((site, here, up) => {
case RocketTilesKey => {
val prev = up(RocketTilesKey, site)
prev.head.copy(
dcache = prev.head.dcache.map(_.copy(nSets = size / site(CacheBlockBytes))),
dataScratchpadBytes = size) +: prev.tail
}
})
// TODO: re-add L2
class WithL2Cache extends Config((site, here, up) => {
case CacheName("L2") => CacheConfig(
nSets = 1024,
nWays = 1,
rowBits = site(L1toL2Config).beatBytes*8,
nTLBEntries = 0,
cacheIdBits = 1,
splitMetadata = false)
})
class WithL2Cache extends Config(Parameters.empty) // TODO: re-add L2
class WithL2Capacity(size_kb: Int) extends Config(Parameters.empty) // TODO: re-add L2
class WithNL2Ways(n: Int) extends Config(Parameters.empty) // TODO: re-add L2
class WithBufferlessBroadcastHub extends Config((site, here, up) => {
case BroadcastConfig => up(BroadcastConfig, site).copy(bufferless = true)
@ -151,44 +130,39 @@ class WithStatelessBridge extends Config((site, here, up) => {
ww.node :*= cork.node
(cork.node, ww.node)
})
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
})
class WithL2Capacity(size_kb: Int) extends Config(Parameters.empty) // TODO
class WithNL2Ways(n: Int) extends Config((site, here, up) => {
case CacheName("L2") => up(CacheName("L2"), site).copy(nWays = n)
})
class WithRV32 extends Config((site, here, up) => {
case XLen => 32
case FPUKey => Some(FPUConfig(divSqrt = false))
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(core = r.core.copy(
mulDiv = Some(MulDivParams(mulUnroll = 8)),
fpu = r.core.fpu.map(_.copy(divSqrt = false))))
}
})
class WithBlockingL1 extends Config((site, here, up) => {
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(dcache = r.dcache.map(_.copy(nMSHRs = 0)))
}
})
class WithSmallCores extends Config((site, here, up) => {
case MulDivKey => Some(MulDivConfig())
case FPUKey => None
case UseVM => false
case BtbKey => BtbParameters(nEntries = 0)
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(core = r.core.copy(nBreakpoints = hwbp))
}
})
class WithRoccExample extends Config((site, here, up) => {
case BuildRoCC => Seq(
RoccParameters(
RoCCParams(
opcodes = OpcodeSet.custom0,
generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
RoccParameters(
RoCCParams(
opcodes = OpcodeSet.custom1,
generator = (p: Parameters) => Module(new TranslatorExample()(p)),
nPTWPorts = 1),
RoccParameters(
RoCCParams(
opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
@ -196,23 +170,34 @@ class WithRoccExample extends Config((site, here, up) => {
})
class WithDefaultBtb extends Config((site, here, up) => {
case BtbKey => BtbParameters()
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(btb = Some(BTBParams()))
}
})
class WithFastMulDiv extends Config((site, here, up) => {
case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true))
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(core = r.core.copy(mulDiv = Some(
MulDivParams(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true)
)))}
})
class WithoutMulDiv extends Config((site, here, up) => {
case MulDivKey => None
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(core = r.core.copy(mulDiv = None))
}
})
class WithoutFPU extends Config((site, here, up) => {
case FPUKey => None
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(core = r.core.copy(fpu = None))
}
})
class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
case FPUKey => Some(FPUConfig(divSqrt = false))
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(core = r.core.copy(fpu = r.core.fpu.map(_.copy(divSqrt = false))))
}
})
class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {

7
src/main/scala/coreplex/RISCVPlatform.scala
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@ -6,14 +6,9 @@ import Chisel._
import config._
import junctions._
import diplomacy._
import uncore.tilelink._
import tile._
import uncore.tilelink2._
import uncore.coherence._
import uncore.agents._
import uncore.devices._
import uncore.util._
import uncore.converters._
import rocket._
import util._
trait CoreplexRISCVPlatform extends CoreplexNetwork {

40
src/main/scala/coreplex/RocketTiles.scala
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@ -6,6 +6,7 @@ import Chisel._
import config._
import diplomacy._
import rocket._
import tile._
import uncore.tilelink2._
sealed trait ClockCrossing
@ -13,18 +14,14 @@ case object Synchronous extends ClockCrossing
case object Rational extends ClockCrossing
case class Asynchronous(depth: Int, sync: Int = 2) extends ClockCrossing
case object RocketConfigs extends Field[Seq[RocketConfig]]
case object RocketTilesKey extends Field[Seq[RocketTileParams]]
case object RocketCrossing extends Field[ClockCrossing]
trait HasRocketTiles extends CoreplexRISCVPlatform {
val module: HasRocketTilesModule
private val crossing = p(RocketCrossing)
private val configs = p(RocketConfigs)
private val pWithExtra = p.alterPartial {
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
case PAddrBits => l1tol2.node.edgesIn(0).bundle.addressBits
}
private val configs = p(RocketTilesKey)
private val rocketTileIntNodes = configs.map { _ => IntInternalOutputNode() }
rocketTileIntNodes.foreach { _ := plic.intnode }
@ -37,11 +34,20 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
}
val rocketWires: Seq[HasRocketTilesBundle => Unit] = configs.zipWithIndex.map { case (c, i) =>
val pWithExtra = p.alterPartial {
case TileKey => c
case BuildRoCC => c.rocc
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
case PAddrBits => l1tol2.node.edgesIn(0).bundle.addressBits
}
crossing match {
case Synchronous => {
val tile = LazyModule(new RocketTile(c)(pWithExtra))
tile.masterNodes.foreach { l1tol2.node := TLBuffer()(_) }
tile.slaveNode.foreach { _ := cbus.node }
val buffer = LazyModule(new TLBuffer)
buffer.node :=* tile.masterNode
l1tol2.node :=* buffer.node
tile.slaveNode :*= cbus.node
(io: HasRocketTilesBundle) => {
// leave clock as default (simpler for hierarchical PnR)
tile.module.io.hartid := UInt(i)
@ -51,8 +57,12 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
}
case Asynchronous(depth, sync) => {
val wrapper = LazyModule(new AsyncRocketTile(c)(pWithExtra))
wrapper.masterNodes.foreach { l1tol2.node := TLAsyncCrossingSink(depth, sync)(_) }
wrapper.slaveNode.foreach { _ := TLAsyncCrossingSource(sync)(cbus.node) }
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
val source = LazyModule(new TLAsyncCrossingSource(sync))
sink.node :=* wrapper.masterNode
l1tol2.node :=* sink.node
wrapper.slaveNode :*= source.node
source.node :*= cbus.node
(io: HasRocketTilesBundle) => {
wrapper.module.clock := io.tcrs(i).clock
wrapper.module.reset := io.tcrs(i).reset
@ -63,8 +73,12 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
}
case Rational => {
val wrapper = LazyModule(new RationalRocketTile(c)(pWithExtra))
wrapper.masterNodes.foreach { l1tol2.node := TLRationalCrossingSink()(_) }
wrapper.slaveNode.foreach { _ := TLRationalCrossingSource()(cbus.node) }
val sink = LazyModule(new TLRationalCrossingSink)
val source = LazyModule(new TLRationalCrossingSource)
sink.node :=* wrapper.masterNode
l1tol2.node :=* sink.node
wrapper.slaveNode :*= source.node
source.node :*= cbus.node
(io: HasRocketTilesBundle) => {
wrapper.module.clock := io.tcrs(i).clock
wrapper.module.reset := io.tcrs(i).reset
@ -79,7 +93,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
trait HasRocketTilesBundle extends CoreplexRISCVPlatformBundle {
val outer: HasRocketTiles
val tcrs = Vec(p(RocketConfigs).size, new Bundle {
val tcrs = Vec(p(RocketTilesKey).size, new Bundle {
val clock = Clock(INPUT)
val reset = Bool(INPUT)
})