diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index 21255209..dd9b9c6e 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -104,6 +104,19 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
   val io: CoreplexNetworkBundle
 
   implicit val p = outer.p
+
+  {
+    println("\nGenerated Address Map")
+    for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) {
+      val prot = (if (manager.supportsGet)     "R" else "") +
+                 (if (manager.supportsPutFull) "W" else "") +
+                 (if (manager.executable)      "X" else "") +
+                 (if (manager.supportsAcquire) " [C]" else "")
+      manager.address.foreach { a =>
+        println(f"\t${manager.name}%s ${a.base}%x - ${a.base+a.mask+1}%x, $prot")
+      }
+    }
+  }
 }
 
 trait BankedL2CoherenceManagers extends CoreplexNetwork {
diff --git a/src/main/scala/coreplex/RISCVPlatform.scala b/src/main/scala/coreplex/RISCVPlatform.scala
index 18fb9368..e379aaeb 100644
--- a/src/main/scala/coreplex/RISCVPlatform.scala
+++ b/src/main/scala/coreplex/RISCVPlatform.scala
@@ -48,25 +48,14 @@ trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule {
   val rtcLast = Reg(init = Bool(false), next=rtcSync)
   outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast)))
 
-  println("\nGenerated Address Map")
-  for (entry <- p(rocketchip.GlobalAddrMap).flatten) {
-    val name = entry.name
-    val start = entry.region.start
-    val end = entry.region.start + entry.region.size - 1
-    val prot = entry.region.attr.prot
-    val protStr = (if ((prot & AddrMapProt.R) > 0) "R" else "") +
-                  (if ((prot & AddrMapProt.W) > 0) "W" else "") +
-                  (if ((prot & AddrMapProt.X) > 0) "X" else "")
-    val cacheable = if (entry.region.attr.cacheable) " [C]" else ""
-    println(f"\t$name%s $start%x - $end%x, $protStr$cacheable")
-  }
+  {
+    val managers = outer.l1tol2.node.edgesIn(0).manager.managers
 
-  // Create and export the ConfigString
-  val managers = outer.l1tol2.node.edgesIn(0).manager.managers
-  val configString = rocketchip.GenerateConfigString(p, outer.clint, outer.plic, managers)
-  // Allow something else to have override the config string
-  if (!ConfigStringOutput.contents.isDefined) {
-    ConfigStringOutput.contents = Some(configString)
+    // Allow something else to have override the config string
+    if (!ConfigStringOutput.contents.isDefined) {
+      ConfigStringOutput.contents = Some(rocketchip.GenerateConfigString(p, outer.clint, outer.plic, managers))
+    }
+
+    println(s"\nGenerated Configuration String\n${ConfigStringOutput.contents.get}")
   }
-  println(s"\nGenerated Configuration String\n${ConfigStringOutput.contents.get}")
 }
diff --git a/src/main/scala/junctions/addrmap.scala b/src/main/scala/junctions/addrmap.scala
index a94ea32d..787f9ab1 100644
--- a/src/main/scala/junctions/addrmap.scala
+++ b/src/main/scala/junctions/addrmap.scala
@@ -8,13 +8,6 @@ import scala.collection.mutable.HashMap
 
 case object PAddrBits extends Field[Int]
 
-trait HasAddrMapParameters {
-  implicit val p: Parameters
-
-  val paddrBits = p(PAddrBits)
-  def addrMap = p(rocketchip.GlobalAddrMap)
-}
-
 case class MemAttr(prot: Int, cacheable: Boolean = false)
 
 sealed abstract class MemRegion {
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index a5f100ab..76055561 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -13,18 +13,11 @@ import util._
 import rocket._
 import coreplex._
 
-// the following parameters will be refactored properly with TL2
-case object GlobalAddrMap extends Field[AddrMap]
 /** Enable or disable monitoring of Diplomatic buses */
 case object TLEmitMonitors extends Field[Boolean]
 
 abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val p: Parameters) extends LazyModule {
-  // Fill in the TL1 legacy parameters; remove these once rocket/groundtest/unittest are TL2
-  lazy val legacyAddrMap = GenerateGlobalAddrMap(p, coreplex.l1tol2.node.edgesIn(0).manager.managers)
-  val coreplex : C = LazyModule(_coreplex(p.alterPartial {
-    case GlobalAddrMap => legacyAddrMap
-  }))
-
+  val coreplex = LazyModule(_coreplex(p))
   TopModule.contents = Some(this)
 }
 
diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala
index f0aaeb9d..f8b3e3f4 100644
--- a/src/main/scala/rocketchip/Utils.scala
+++ b/src/main/scala/rocketchip/Utils.scala
@@ -52,36 +52,6 @@ class GlobalVariable[T] {
   def get: T = { require(assigned); variable }
 }
 
-object GenerateGlobalAddrMap {
-  def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = {
-    val tl2Devices = peripheryManagers.map { manager =>
-      val cacheable = manager.regionType match {
-        case RegionType.CACHED   => true
-        case RegionType.TRACKED  => true
-        case _ => false
-      }
-      val attr = MemAttr(
-        (if (manager.supportsGet)     AddrMapProt.R else 0) |
-        (if (manager.supportsPutFull) AddrMapProt.W else 0) |
-        (if (manager.executable)      AddrMapProt.X else 0), cacheable)
-      val multi = manager.address.size > 1
-      manager.address.zipWithIndex.map { case (address, i) =>
-        require (address.contiguous) // TL1 needs this
-        val name = manager.name + (if (multi) ".%d".format(i) else "")
-        AddrMapEntry(name, MemRange(address.base, address.mask+1, attr))
-      }
-    }.flatten
-
-    val uniquelyNamedTL2Devices =
-      tl2Devices.groupBy(_.name).values.map(_.zipWithIndex.map {
-        case (e, i) => if (i == 0) e else e.copy(name = e.name + "_" + i)
-      }).flatten.toList
-
-    val tl2 = AddrMapEntry("TL2", new AddrMap(uniquelyNamedTL2Devices, collapse = true))
-    AddrMap(tl2)
-  }
-}
-
 object GenerateConfigString {
   def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = {
     val c = CoreplexParameters()(p)