riscv/rocket-chip
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Clean up formatting (i.e. remove tabs, semicolons)

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This commit is contained in:
Andrew Waterman
2014-01-13 21:43:56 -08:00
parent a50a1f7d50
commit e8486817e6
7 changed files with 93 additions and 93 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@ -808,7 +808,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
val misaligned =
(((s1_req.typ === MT_H) || (s1_req.typ === MT_HU)) && (s1_req.addr(0) != Bits(0))) ||
(((s1_req.typ === MT_W) || (s1_req.typ === MT_WU)) && (s1_req.addr(1,0) != Bits(0))) ||
((s1_req.typ === MT_D) && (s1_req.addr(2,0) != Bits(0)));
((s1_req.typ === MT_D) && (s1_req.addr(2,0) != Bits(0)))
io.cpu.xcpt.ma.ld := s1_read && misaligned
io.cpu.xcpt.ma.st := s1_write && misaligned