riscv/rocket-chip
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Clean up formatting (i.e. remove tabs, semicolons)

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This commit is contained in:
Andrew Waterman
2014-01-13 21:43:56 -08:00
parent a50a1f7d50
commit e8486817e6
7 changed files with 93 additions and 93 deletions
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14
rocket/src/main/scala/consts.scala
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@@ -27,12 +27,12 @@ trait ScalarOpConstants {
val A1_PC = UInt(3, 2)
val IMM_X = Bits("b???", 3)
val IMM_S = UInt(0, 3);
val IMM_SB = UInt(1, 3);
val IMM_U = UInt(2, 3);
val IMM_UJ = UInt(3, 3);
val IMM_I = UInt(4, 3);
val IMM_Z = UInt(5, 3);
val IMM_S = UInt(0, 3)
val IMM_SB = UInt(1, 3)
val IMM_U = UInt(2, 3)
val IMM_UJ = UInt(3, 3)
val IMM_I = UInt(4, 3)
val IMM_Z = UInt(5, 3)
val A2_X = Bits("b??", 2)
val A2_ZERO = UInt(0, 2)
@@ -57,7 +57,7 @@ trait ScalarOpConstants {
val DW_64 = Y
val DW_XPR = Y
val RA = UInt(1, 5);
val RA = UInt(1, 5)
}
trait InterruptConstants {

102
rocket/src/main/scala/ctrl.scala
View File

@@ -9,8 +9,8 @@ import Util._
class CtrlDpathIO extends Bundle()
{
// outputs to datapath
val sel_pc = UInt(OUTPUT, 3);
val killd = Bool(OUTPUT);
val sel_pc = UInt(OUTPUT, 3)
val killd = Bool(OUTPUT)
val ren = Vec.fill(2)(Bool(OUTPUT))
val sel_alu2 = UInt(OUTPUT, 3)
val sel_alu1 = UInt(OUTPUT, 2)
@@ -19,19 +19,19 @@ class CtrlDpathIO extends Bundle()
val fn_alu = UInt(OUTPUT, SZ_ALU_FN)
val div_mul_val = Bool(OUTPUT)
val div_mul_kill = Bool(OUTPUT)
val div_val = Bool(OUTPUT);
val div_val = Bool(OUTPUT)
val div_kill = Bool(OUTPUT)
val csr = UInt(OUTPUT, 3)
val sret = Bool(OUTPUT)
val mem_load = Bool(OUTPUT);
val mem_load = Bool(OUTPUT)
val wb_load = Bool(OUTPUT)
val ex_fp_val= Bool(OUTPUT);
val mem_fp_val= Bool(OUTPUT);
val ex_wen = Bool(OUTPUT);
val ex_fp_val= Bool(OUTPUT)
val mem_fp_val= Bool(OUTPUT)
val ex_wen = Bool(OUTPUT)
val ex_jalr = Bool(OUTPUT)
val ex_predicted_taken = Bool(OUTPUT)
val mem_wen = Bool(OUTPUT);
val wb_wen = Bool(OUTPUT);
val mem_wen = Bool(OUTPUT)
val wb_wen = Bool(OUTPUT)
val ex_mem_type = Bits(OUTPUT, 3)
val ex_rs2_val = Bool(OUTPUT)
val ex_rocc_val = Bool(OUTPUT)
@@ -41,11 +41,11 @@ class CtrlDpathIO extends Bundle()
val ll_ready = Bool(OUTPUT)
// exception handling
val retire = Bool(OUTPUT)
val exception = Bool(OUTPUT);
val cause = UInt(OUTPUT, 6);
val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault
val exception = Bool(OUTPUT)
val cause = UInt(OUTPUT, 6)
val badvaddr_wen = Bool(OUTPUT) // high for a load/store access fault
// inputs from datapath
val inst = Bits(INPUT, 32);
val inst = Bits(INPUT, 32)
val jalr_eq = Bool(INPUT)
val ex_br_type = Bits(OUTPUT, SZ_BR)
val ex_br_taken = Bool(INPUT)
@@ -56,14 +56,14 @@ class CtrlDpathIO extends Bundle()
val mem_waddr = UInt(INPUT, 5)
val wb_waddr = UInt(INPUT, 5)
val status = new Status().asInput
val fp_sboard_clr = Bool(INPUT);
val fp_sboard_clra = UInt(INPUT, 5);
val fp_sboard_clr = Bool(INPUT)
val fp_sboard_clra = UInt(INPUT, 5)
val csr_replay = Bool(INPUT)
}
abstract trait DecodeConstants
{
val xpr64 = Y;
val xpr64 = Y
val decode_default =
// fence.i
@@ -446,14 +446,14 @@ class Control(implicit conf: RocketConfiguration) extends Module
when (ctrl_killd) {
ex_reg_jalr := Bool(false)
ex_reg_btb_hit := Bool(false);
ex_reg_btb_hit := Bool(false)
ex_reg_div_mul_val := Bool(false)
ex_reg_mem_val := Bool(false);
ex_reg_valid := Bool(false);
ex_reg_wen := Bool(false);
ex_reg_fp_wen := Bool(false);
ex_reg_mem_val := Bool(false)
ex_reg_valid := Bool(false)
ex_reg_wen := Bool(false)
ex_reg_fp_wen := Bool(false)
ex_reg_sret := Bool(false)
ex_reg_flush_inst := Bool(false);
ex_reg_flush_inst := Bool(false)
ex_reg_fp_val := Bool(false)
ex_reg_rocc_val := Bool(false)
ex_reg_replay_next := Bool(false)
@@ -463,11 +463,11 @@ class Control(implicit conf: RocketConfiguration) extends Module
ex_reg_xcpt := Bool(false)
}
.otherwise {
ex_reg_br_type := id_br_type;
ex_reg_br_type := id_br_type
ex_reg_jalr := id_jalr
ex_reg_btb_hit := io.imem.resp.bits.taken && !id_jalr
ex_reg_div_mul_val := id_mul_val || id_div_val
ex_reg_mem_val := id_mem_val.toBool;
ex_reg_mem_val := id_mem_val.toBool
ex_reg_valid := Bool(true)
ex_reg_csr := id_csr
ex_reg_wen := id_wen
@@ -498,19 +498,19 @@ class Control(implicit conf: RocketConfiguration) extends Module
(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause),
(ex_reg_fp_val && io.fpu.illegal_rm, UInt(2))))
mem_reg_replay := replay_ex && !take_pc_wb;
mem_reg_replay := replay_ex && !take_pc_wb
mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb && !mem_reg_replay_next
when (ex_xcpt) { mem_reg_cause := ex_cause }
mem_reg_div_mul_val := ex_reg_div_mul_val && io.dpath.div_mul_rdy
when (ctrl_killx) {
mem_reg_valid := Bool(false);
mem_reg_valid := Bool(false)
mem_reg_csr := CSR.N
mem_reg_wen := Bool(false);
mem_reg_fp_wen := Bool(false);
mem_reg_wen := Bool(false)
mem_reg_fp_wen := Bool(false)
mem_reg_sret := Bool(false)
mem_reg_mem_val := Bool(false);
mem_reg_flush_inst := Bool(false);
mem_reg_mem_val := Bool(false)
mem_reg_flush_inst := Bool(false)
mem_reg_fp_val := Bool(false)
mem_reg_rocc_val := Bool(false)
mem_reg_replay_next := Bool(false)
@@ -519,11 +519,11 @@ class Control(implicit conf: RocketConfiguration) extends Module
.otherwise {
mem_reg_valid := ex_reg_valid
mem_reg_csr := ex_reg_csr
mem_reg_wen := ex_reg_wen;
mem_reg_fp_wen := ex_reg_fp_wen;
mem_reg_wen := ex_reg_wen
mem_reg_fp_wen := ex_reg_fp_wen
mem_reg_sret := ex_reg_sret
mem_reg_mem_val := ex_reg_mem_val;
mem_reg_flush_inst := ex_reg_flush_inst;
mem_reg_mem_val := ex_reg_mem_val
mem_reg_flush_inst := ex_reg_flush_inst
mem_reg_fp_val := ex_reg_fp_val
mem_reg_rocc_val := ex_reg_rocc_val
mem_reg_replay_next := ex_reg_replay_next
@@ -550,22 +550,22 @@ class Control(implicit conf: RocketConfiguration) extends Module
when (ctrl_killm) {
wb_reg_valid := Bool(false)
wb_reg_csr := CSR.N
wb_reg_wen := Bool(false);
wb_reg_fp_wen := Bool(false);
wb_reg_wen := Bool(false)
wb_reg_fp_wen := Bool(false)
wb_reg_sret := Bool(false)
wb_reg_flush_inst := Bool(false);
wb_reg_flush_inst := Bool(false)
wb_reg_mem_val := Bool(false)
wb_reg_div_mul_val := Bool(false);
wb_reg_div_mul_val := Bool(false)
wb_reg_fp_val := Bool(false)
wb_reg_rocc_val := Bool(false)
}
.otherwise {
wb_reg_valid := mem_reg_valid
wb_reg_csr := mem_reg_csr
wb_reg_wen := mem_reg_wen;
wb_reg_fp_wen := mem_reg_fp_wen;
wb_reg_wen := mem_reg_wen
wb_reg_fp_wen := mem_reg_fp_wen
wb_reg_sret := mem_reg_sret && !mem_reg_replay
wb_reg_flush_inst := mem_reg_flush_inst;
wb_reg_flush_inst := mem_reg_flush_inst
wb_reg_mem_val := mem_reg_mem_val
wb_reg_div_mul_val := mem_reg_div_mul_val
wb_reg_fp_val := mem_reg_fp_val
@@ -613,14 +613,14 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.fpu.dec.wen && fp_sboard.read(id_waddr)
} else Bool(false)
// write CAUSE CSR on an exception
io.dpath.exception := wb_reg_xcpt
io.dpath.cause := wb_reg_cause
io.dpath.badvaddr_wen := wb_reg_xcpt // don't care for non-memory exceptions
// write CAUSE CSR on an exception
io.dpath.exception := wb_reg_xcpt
io.dpath.cause := wb_reg_cause
io.dpath.badvaddr_wen := wb_reg_xcpt // don't care for non-memory exceptions
// control transfer from ex/wb
take_pc_wb := replay_wb || wb_reg_xcpt || wb_reg_sret
take_pc := take_pc_ex || take_pc_wb;
take_pc := take_pc_ex || take_pc_wb
io.dpath.sel_pc :=
Mux(wb_reg_xcpt, PC_PCR, // exception
@@ -706,16 +706,16 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.dpath.sel_alu2 := id_sel_alu2.toUInt
io.dpath.sel_alu1 := id_sel_alu1.toUInt
io.dpath.sel_imm := id_sel_imm.toUInt
io.dpath.fn_dw := id_fn_dw.toBool;
io.dpath.fn_dw := id_fn_dw.toBool
io.dpath.fn_alu := id_fn_alu.toUInt
io.dpath.div_mul_val := ex_reg_div_mul_val
io.dpath.div_mul_kill := mem_reg_div_mul_val && killm_common
io.dpath.ex_fp_val:= ex_reg_fp_val;
io.dpath.mem_fp_val:= mem_reg_fp_val;
io.dpath.ex_fp_val:= ex_reg_fp_val
io.dpath.mem_fp_val:= mem_reg_fp_val
io.dpath.ex_jalr := ex_reg_jalr
io.dpath.ex_predicted_taken := ex_reg_btb_hit
io.dpath.ex_wen := ex_reg_wen;
io.dpath.mem_wen := mem_reg_wen;
io.dpath.ex_wen := ex_reg_wen
io.dpath.mem_wen := mem_reg_wen
io.dpath.ll_ready := !wb_reg_wen
io.dpath.wb_wen := wb_reg_wen && !replay_wb
io.dpath.retire := wb_reg_valid && !replay_wb

10
rocket/src/main/scala/dpath.scala
View File

@@ -145,8 +145,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
A2_FOUR -> SInt(4)))
val alu = Module(new ALU)
alu.io.dw := ex_reg_ctrl_fn_dw;
alu.io.fn := ex_reg_ctrl_fn_alu;
alu.io.dw := ex_reg_ctrl_fn_dw
alu.io.fn := ex_reg_ctrl_fn_alu
alu.io.in2 := ex_op2.toUInt
alu.io.in1 := ex_op1
@@ -185,7 +185,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
require(io.dmem.req.bits.tag.getWidth >= 6)
// processor control regfile read
// processor control regfile read
val pcr = Module(new CSRFile)
pcr.io.host <> io.host
pcr.io <> io.ctrl
@@ -198,7 +198,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
io.ptw.sret := io.ctrl.sret
io.ptw.status := pcr.io.status
// branch resolution logic
// branch resolution logic
io.ctrl.jalr_eq := ex_rs(0) === id_pc.toSInt && ex_reg_inst(31,20) === UInt(0)
io.ctrl.ex_br_taken :=
Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs(0) === ex_rs(1),
@@ -278,7 +278,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
io.ctrl.fp_sboard_clr := dmem_resp_replay && dmem_resp_fpu
io.ctrl.fp_sboard_clra := dmem_resp_waddr
// processor control regfile write
// processor control regfile write
pcr.io.rw.addr := wb_reg_inst(31,20)
pcr.io.rw.cmd := io.ctrl.csr
pcr.io.rw.wdata := wb_reg_wdata

24
rocket/src/main/scala/dpath_util.scala
View File

@@ -9,14 +9,14 @@ import scala.math._
class DpathBTBIO extends Bundle
{
val current_pc = UInt(INPUT, VADDR_BITS);
val hit = Bool(OUTPUT);
val target = UInt(OUTPUT, VADDR_BITS);
val wen = Bool(INPUT);
val clr = Bool(INPUT);
val invalidate = Bool(INPUT);
val correct_pc = UInt(INPUT, VADDR_BITS);
val correct_target = UInt(INPUT, VADDR_BITS);
val current_pc = UInt(INPUT, VADDR_BITS)
val hit = Bool(OUTPUT)
val target = UInt(OUTPUT, VADDR_BITS)
val wen = Bool(INPUT)
val clr = Bool(INPUT)
val invalidate = Bool(INPUT)
val correct_pc = UInt(INPUT, VADDR_BITS)
val correct_target = UInt(INPUT, VADDR_BITS)
}
// fully-associative branch target buffer
@@ -265,13 +265,13 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
when (decoded_addr(CSRs.epc)) { reg_epc := wdata(VADDR_BITS,0).toSInt }
when (decoded_addr(CSRs.evec)) { reg_evec := wdata(VADDR_BITS-1,0).toSInt }
when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt }
when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false); }
when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) }
when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } }
when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) }
when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata; }
when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata; }
when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt; }
when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata }
when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata }
when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt }
when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
}
}

2
rocket/src/main/scala/nbdcache.scala
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@@ -808,7 +808,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
val misaligned =
(((s1_req.typ === MT_H) || (s1_req.typ === MT_HU)) && (s1_req.addr(0) != Bits(0))) ||
(((s1_req.typ === MT_W) || (s1_req.typ === MT_WU)) && (s1_req.addr(1,0) != Bits(0))) ||
((s1_req.typ === MT_D) && (s1_req.addr(2,0) != Bits(0)));
((s1_req.typ === MT_D) && (s1_req.addr(2,0) != Bits(0)))
io.cpu.xcpt.ma.ld := s1_read && misaligned
io.cpu.xcpt.ma.st := s1_write && misaligned

8
rocket/src/main/scala/ptw.scala
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@@ -91,13 +91,13 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
switch (state) {
is (s_ready) {
when (arb.io.out.valid) {
state := s_req;
state := s_req
}
count := UInt(0)
}
is (s_req) {
when (io.mem.req.ready) {
state := s_wait;
state := s_wait
}
}
is (s_wait) {
@@ -117,10 +117,10 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
}
}
is (s_done) {
state := s_ready;
state := s_ready
}
is (s_error) {
state := s_ready;
state := s_ready
}
}
}

26
rocket/src/main/scala/tlb.scala
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@@ -5,30 +5,30 @@ import uncore.constants.AddressConstants._
import scala.math._
class CAMIO(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
val clear = Bool(INPUT);
val clear = Bool(INPUT)
val clear_hit = Bool(INPUT)
val tag = Bits(INPUT, tag_bits);
val hit = Bool(OUTPUT);
val hits = UInt(OUTPUT, entries);
val valid_bits = Bits(OUTPUT, entries);
val tag = Bits(INPUT, tag_bits)
val hit = Bool(OUTPUT)
val hits = UInt(OUTPUT, entries)
val valid_bits = Bits(OUTPUT, entries)
val write = Bool(INPUT);
val write_tag = Bits(INPUT, tag_bits);
val write_addr = UInt(INPUT, addr_bits);
val write = Bool(INPUT)
val write_tag = Bits(INPUT, tag_bits)
val write_addr = UInt(INPUT, addr_bits)
}
class RocketCAM(entries: Int, tag_bits: Int) extends Module {
val addr_bits = ceil(log(entries)/log(2)).toInt;
val io = new CAMIO(entries, addr_bits, tag_bits);
val addr_bits = ceil(log(entries)/log(2)).toInt
val io = new CAMIO(entries, addr_bits, tag_bits)
val cam_tags = Mem(Bits(width = tag_bits), entries)
val vb_array = Reg(init=Bits(0, entries))
when (io.write) {
vb_array := vb_array.bitSet(io.write_addr, Bool(true));
vb_array := vb_array.bitSet(io.write_addr, Bool(true))
cam_tags(io.write_addr) := io.write_tag
}
when (io.clear) {
vb_array := Bits(0, entries);
vb_array := Bits(0, entries)
}
.elsewhen (io.clear_hit) {
vb_array := vb_array & ~io.hits
@@ -36,7 +36,7 @@ class RocketCAM(entries: Int, tag_bits: Int) extends Module {
val hits = (0 until entries).map(i => vb_array(i) && cam_tags(i) === io.tag)
io.valid_bits := vb_array;
io.valid_bits := vb_array
io.hits := Vec(hits).toBits
io.hit := io.hits.orR
}