From e8408f0a8a8059751618d6b3224a4de05a5e11be Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 1 Jun 2016 10:33:59 -0700 Subject: [PATCH] fix HastiRAM --- uncore/src/main/scala/bram.scala | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/uncore/src/main/scala/bram.scala b/uncore/src/main/scala/bram.scala index 76af2802..480f4a73 100644 --- a/uncore/src/main/scala/bram.scala +++ b/uncore/src/main/scala/bram.scala @@ -76,15 +76,13 @@ class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) { val max_wsize = log2Ceil(hastiDataBytes) val wmask_lut = MuxLookup(wsize, SInt(-1, hastiDataBytes).asUInt, - (0 until max_wsize).map(1 << _).map(sz => (UInt(sz) -> UInt((1 << sz << sz) - 1)))) + (0 until max_wsize).map(sz => (UInt(sz) -> UInt((1 << (1 << sz)) - 1)))) val wmask = (wmask_lut << waddr(max_wsize - 1, 0))(hastiDataBytes - 1, 0) val is_trans = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ) val raddr = io.haddr >> UInt(2) val ren = is_trans && !io.hwrite val bypass = Reg(init = Bool(false)) - val last_wdata = Reg(next = wdata) - val last_wmask = Reg(next = wmask) when (is_trans && io.hwrite) { waddr := io.haddr