riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

turn up generator memory timeout

Browse Source
This commit is contained in:
Howard Mao 2016-06-29 10:57:31 -07:00
parent 80670c08d7
commit e83b3d2472
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
groundtest/src/main/scala/generator.scala
View File

@ -15,7 +15,7 @@ case object GeneratorStartAddress extends Field[BigInt]
trait HasGeneratorParameters extends HasGroundTestParameters { trait HasGeneratorParameters extends HasGroundTestParameters {
implicit val p: Parameters implicit val p: Parameters
val nGens = p(NTiles) * (nUncached + nCached) val nGens = p(NTiles) * (nUncached + nCached)
val genTimeout = 4096 val genTimeout = 8192
val maxRequests = p(MaxGenerateRequests) val maxRequests = p(MaxGenerateRequests)
val startAddress = p(GeneratorStartAddress) val startAddress = p(GeneratorStartAddress)
val genWordBits = 32 val genWordBits = 32
@ -114,8 +114,8 @@ class UncachedTileLinkGenerator(id: Int)
class HellaCacheGenerator(id: Int) class HellaCacheGenerator(id: Int)
(implicit p: Parameters) extends L1HellaCacheModule()(p) with HasGeneratorParameters { (implicit p: Parameters) extends L1HellaCacheModule()(p) with HasGeneratorParameters {
val io = new Bundle { val io = new Bundle {
val finished = Bool(OUTPUT)
val mem = new HellaCacheIO val mem = new HellaCacheIO
val finished = Bool(OUTPUT)
} }
val timeout = Timer(genTimeout, io.mem.req.fire(), io.mem.resp.valid) val timeout = Timer(genTimeout, io.mem.req.fire(), io.mem.resp.valid)