Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.

This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.

vsim/Makefrag

@@ -16,13 +16,15 @@ sim_vsrcs = \
 	$(generated_dir)/$(long_name).behav_srams.v \
 	$(base_dir)/vsrc/$(TB).v \
 	$(base_dir)/vsrc/SimDTM.v \
+        $(base_dir)/vsrc/SimJTAG.v \
 	$(bb_vsrcs)
 
 # C sources
 
 sim_csrcs = \
 	$(base_dir)/csrc/SimDTM.cc \
-	$(base_dir)/csrc/jtag_vpi.c
+        $(base_dir)/csrc/SimJTAG.cc \
+        $(base_dir)/csrc/remote_bitbang.cc \
 
 #--------------------------------------------------------------------
 # Build Verilog