riscv/rocket-chip
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Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.

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This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
This commit is contained in:
Megan Wachs
2017-04-11 20:03:34 -07:00
parent 206892899f
commit e82328336e
9 changed files with 430 additions and 23 deletions
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4
vsim/Makefrag
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@ -16,13 +16,15 @@ sim_vsrcs = \
$(generated_dir)/$(long_name).behav_srams.v \
$(base_dir)/vsrc/$(TB).v \
$(base_dir)/vsrc/SimDTM.v \
$(base_dir)/vsrc/SimJTAG.v \
$(bb_vsrcs)
# C sources
sim_csrcs = \
$(base_dir)/csrc/SimDTM.cc \
$(base_dir)/csrc/jtag_vpi.c
$(base_dir)/csrc/SimJTAG.cc \
$(base_dir)/csrc/remote_bitbang.cc \
#--------------------------------------------------------------------
# Build Verilog