Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.

This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.

src/main/scala/system/Configs.scala

@@ -9,6 +9,8 @@ import freechips.rocketchip.coreplex._
 import freechips.rocketchip.devices.debug.{IncludeJtagDTM, JtagDTMKey}
 import freechips.rocketchip.diplomacy._
 
+class WithJtagDTMSystem extends freechips.rocketchip.coreplex.WithJtagDTM
+
 class BaseConfig extends Config(new BaseCoreplexConfig().alter((site,here,up) => {
   // DTS descriptive parameters
   case DTSModel => "freechips,rocketchip-unknown"