riscv/rocket-chip
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Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.

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This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
This commit is contained in:
Megan Wachs
2017-04-11 20:03:34 -07:00
parent 206892899f
commit e82328336e
9 changed files with 430 additions and 23 deletions
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14
csrc/emulator.cc
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@ -6,6 +6,7 @@
#include "verilated_vcd_c.h"
#endif
#include <fesvr/dtm.h>
#include "remote_bitbang.h"
#include <iostream>
#include <fcntl.h>
#include <signal.h>
@ -15,6 +16,8 @@
#include <getopt.h>
extern dtm_t* dtm;
extern remote_bitbang_t * jtag;
static uint64_t trace_count = 0;
bool verbose;
bool done_reset;
@ -169,6 +172,8 @@ done_processing:
#endif
dtm = new dtm_t(to_dtm);
//TODO: Specify port.
jtag = new remote_bitbang_t(0);
signal(SIGTERM, handle_sigterm);
@ -183,7 +188,8 @@ done_processing:
}
done_reset = true;
while (!dtm->done() && !tile->io_success && trace_count < max_cycles) {
while (!dtm->done() && !jtag->done() &&
!tile->io_success && trace_count < max_cycles) {
tile->clock = 0;
tile->eval();
#if VM_TRACE
@ -213,6 +219,11 @@ done_processing:
fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count);
ret = dtm->exit_code();
}
else if (jtag->exit_code())
{
fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", jtag->exit_code(), random_seed, trace_count);
ret = jtag->exit_code();
}
else if (trace_count == max_cycles)
{
fprintf(stderr, "*** FAILED *** (timeout, seed %d) after %ld cycles\n", random_seed, trace_count);
@ -224,6 +235,7 @@ done_processing:
}
if (dtm) delete dtm;
if (jtag) delete jtag;
if (tile) delete tile;
return ret;
}