riscv/rocket-chip
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remove more global constants

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This commit is contained in:
Andrew Waterman 2012-11-06 02:55:45 -08:00
parent c5b93798fb
commit e76892f758
4 changed files with 42 additions and 84 deletions
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5
rocket/src/main/scala/consts.scala
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@ -198,11 +198,6 @@ trait VectorOpConstants {
}
abstract trait ArbiterConstants extends TileConfigConstants {
val DTLB_PORTS = 3
val DTLB_CPU = 0
val DTLB_VEC = 1
val DTLB_VPF = 2
val DCACHE_PORTS = 3
val DCACHE_CPU = 0
val DCACHE_PTW = 1

100
rocket/src/main/scala/cpu.scala
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@ -20,57 +20,40 @@ class rocketProc(implicit conf: RocketConfiguration) extends Component
val ctrl = new Control
val dpath = new Datapath
val dtlb = new rocketTLB(DTLB_ENTRIES);
val ptw = new rocketPTW(if (HAVE_VEC) 3 else 2)
val ptw = Vec(0) { new IOTLBPTW }
val arb = new HellaCacheArbiter(DCACHE_PORTS)
var vu: vu = null
if (HAVE_VEC)
{
vu = new vu()
// cpu, vector prefetch, and vector use the DTLB
val dtlbarb = new RRArbiter(DTLB_PORTS)({new ioDTLB_CPU_req_bundle()})
val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2Up(DTLB_PORTS)))
when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }
// tlb respones come out a cycle later
val chosen_vec = dtlbchosen === Bits(DTLB_VEC)
val chosen_pf = dtlbchosen === Bits(DTLB_VPF)
val chosen_cpu = dtlbchosen === Bits(DTLB_CPU)
val vdtlb = new rocketTLB(8)
vdtlb.io.invalidate := dpath.io.ptbr_wen
vdtlb.io.status := dpath.io.ctrl.status
ptw += vdtlb.io.ptw
dtlbarb.io.in(DTLB_VEC) <> vu.io.vec_tlb_req
vu.io.vec_tlb_resp.xcpt_ld := chosen_vec && dtlb.io.cpu_resp.xcpt_ld
vu.io.vec_tlb_resp.xcpt_st := chosen_vec && dtlb.io.cpu_resp.xcpt_st
vdtlb.io.cpu_req <> vu.io.vec_tlb_req
vu.io.vec_tlb_resp := vdtlb.io.cpu_resp
vu.io.vec_tlb_resp.xcpt_pf := Bool(false)
vu.io.vec_tlb_resp.miss := chosen_vec && dtlb.io.cpu_resp.miss
vu.io.vec_tlb_resp.ppn := dtlb.io.cpu_resp.ppn
dtlbarb.io.in(DTLB_VPF) <> vu.io.vec_pftlb_req
val pftlb = new rocketTLB(2)
pftlb.io.invalidate := dpath.io.ptbr_wen
pftlb.io.status := dpath.io.ctrl.status
pftlb.io.cpu_req <> vu.io.vec_pftlb_req
ptw += pftlb.io.ptw
vu.io.vec_pftlb_resp := pftlb.io.cpu_resp
vu.io.vec_pftlb_resp.xcpt_ld := Bool(false)
vu.io.vec_pftlb_resp.xcpt_st := Bool(false)
vu.io.vec_pftlb_resp.xcpt_pf := chosen_pf && dtlb.io.cpu_resp.xcpt_pf
vu.io.vec_pftlb_resp.miss := chosen_pf && dtlb.io.cpu_resp.miss
vu.io.vec_pftlb_resp.ppn := dtlb.io.cpu_resp.ppn
// connect DTLB to ctrl+dpath
dtlbarb.io.in(DTLB_CPU).valid := ctrl.io.dtlb_val
dtlbarb.io.in(DTLB_CPU).bits.kill := ctrl.io.dtlb_kill
dtlbarb.io.in(DTLB_CPU).bits.cmd := ctrl.io.dmem.req.bits.cmd
dtlbarb.io.in(DTLB_CPU).bits.asid := UFix(0)
dtlbarb.io.in(DTLB_CPU).bits.vpn := dpath.io.dtlb.vpn
ctrl.io.dtlb_rdy := dtlbarb.io.in(DTLB_CPU).ready
ctrl.io.xcpt_dtlb_ld := chosen_cpu && dtlb.io.cpu_resp.xcpt_ld
ctrl.io.xcpt_dtlb_st := chosen_cpu && dtlb.io.cpu_resp.xcpt_st
ctrl.io.dtlb_miss := chosen_cpu && dtlb.io.cpu_resp.miss
dtlb.io.cpu_req <> dtlbarb.io.out
}
else
{
// connect DTLB to ctrl+dpath
val dtlb = new rocketTLB(DTLB_ENTRIES)
dtlb.io.invalidate := dpath.io.ptbr_wen
dtlb.io.status := dpath.io.ctrl.status
ptw += dtlb.io.ptw
dtlb.io.cpu_req.valid := ctrl.io.dtlb_val
dtlb.io.cpu_req.bits.kill := ctrl.io.dtlb_kill
dtlb.io.cpu_req.bits.cmd := ctrl.io.dmem.req.bits.cmd
@ -80,44 +63,17 @@ class rocketProc(implicit conf: RocketConfiguration) extends Component
ctrl.io.xcpt_dtlb_st := dtlb.io.cpu_resp.xcpt_st
ctrl.io.dtlb_rdy := dtlb.io.cpu_req.ready
ctrl.io.dtlb_miss := dtlb.io.cpu_resp.miss
}
dtlb.io.invalidate := dpath.io.ptbr_wen
dtlb.io.status := dpath.io.ctrl.status
arb.io.requestor(DCACHE_CPU).req.bits.ppn := dtlb.io.cpu_resp.ppn
ctrl.io.dmem.req.ready := dtlb.io.cpu_req.ready && arb.io.requestor(DCACHE_CPU).req.ready
// connect page table walker to TLBs, page table base register (from PCR)
// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
ptw.io.requestor(0) <> io.imem.ptw
ptw.io.requestor(1) <> dtlb.io.ptw
ptw.io.ptbr := dpath.io.ptbr;
arb.io.requestor(DCACHE_PTW) <> ptw.io.mem
arb.io.mem <> io.dmem
ctrl.io.dpath <> dpath.io.ctrl
dpath.io.host <> io.host
ctrl.io.dpath <> dpath.io.ctrl;
dpath.io.host <> io.host;
// FIXME: try to make this more compact
// connect I$
ctrl.io.imem <> io.imem
dpath.io.imem <> io.imem
// connect arbiter to ctrl+dpath+DTLB
//TODO: views on nested bundles?
arb.io.requestor(DCACHE_CPU).resp <> ctrl.io.dmem.resp
arb.io.requestor(DCACHE_CPU).xcpt <> ctrl.io.dmem.xcpt
arb.io.requestor(DCACHE_CPU).resp <> dpath.io.dmem.resp
arb.io.requestor(DCACHE_CPU).req.valid := ctrl.io.dmem.req.valid
ctrl.io.dmem.req.ready := arb.io.requestor(DCACHE_CPU).req.ready
arb.io.requestor(DCACHE_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill
arb.io.requestor(DCACHE_CPU).req.bits.cmd := ctrl.io.dmem.req.bits.cmd
arb.io.requestor(DCACHE_CPU).req.bits.typ := ctrl.io.dmem.req.bits.typ
arb.io.requestor(DCACHE_CPU).req.bits.idx := dpath.io.dmem.req.bits.idx
arb.io.requestor(DCACHE_CPU).req.bits.tag := dpath.io.dmem.req.bits.tag
arb.io.requestor(DCACHE_CPU).req.bits.data := dpath.io.dmem.req.bits.data
ctrl.io.dmem <> arb.io.requestor(DCACHE_CPU)
dpath.io.dmem <> arb.io.requestor(DCACHE_CPU)
var fpu: rocketFPU = null
if (HAVE_FPU)
@ -132,7 +88,7 @@ class rocketProc(implicit conf: RocketConfiguration) extends Component
dpath.io.vec_ctrl <> ctrl.io.vec_dpath
// hooking up vector I$
ptw.io.requestor(2) <> io.vimem.ptw
ptw += io.vimem.ptw
io.vimem.req.bits.status := dpath.io.ctrl.status
io.vimem.req.bits.pc := vu.io.imem_req.bits
io.vimem.req.valid := vu.io.imem_req.valid
@ -232,4 +188,12 @@ class rocketProc(implicit conf: RocketConfiguration) extends Component
fpu.io.dfma.valid := Bool(false)
}
}
ptw += io.imem.ptw
val thePTW = new PTW(ptw.length)
thePTW.io.requestor <> ptw
thePTW.io.ptbr := dpath.io.ptbr;
arb.io.requestor(DCACHE_PTW) <> thePTW.io.mem
arb.io.mem <> io.dmem
}

1
rocket/src/main/scala/ctrl.scala
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@ -735,7 +735,6 @@ class Control(implicit conf: RocketConfiguration) extends Component
id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr ||
id_fp_val && id_stall_fpu ||
id_mem_val && !(io.dmem.req.ready && io.dtlb_rdy) ||
(id_sync === SYNC_D || id_sync === SYNC_I) && !io.dmem.req.ready ||
vec_stalld
ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || id_interrupt

4
rocket/src/main/scala/ptw.scala
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@ -12,7 +12,7 @@ class ioPTW(n: Int)(implicit conf: RocketConfiguration) extends Bundle
val ptbr = UFix(INPUT, PADDR_BITS)
}
class rocketPTW(n: Int)(implicit conf: RocketConfiguration) extends Component
class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
{
val io = new ioPTW(n)
@ -34,7 +34,7 @@ class rocketPTW(n: Int)(implicit conf: RocketConfiguration) extends Component
val vpn_idxs = (1 until levels).map(i => r_req_vpn((levels-i)*bitsPerLevel-1, (levels-i-1)*bitsPerLevel))
val vpn_idx = (2 until levels).foldRight(vpn_idxs(0))((i,j) => Mux(count === UFix(i-1), vpn_idxs(i-1), j))
val arb = new Arbiter(n)(UFix(width = VPN_BITS))
val arb = new RRArbiter(n)(UFix(width = VPN_BITS))
arb.io.in <> io.requestor.map(_.req)
arb.io.out.ready := state === s_ready