riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

ROM: optionally (default: true) executable

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-09-17 00:19:09 -07:00
parent c70045b8b3
commit e749558190
1 changed files with 2 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/uncore/devices/Rom.scala
View File

@@ -8,11 +8,12 @@ import uncore.tilelink2._
import uncore.util._ import uncore.util._
import cde.{Parameters, Field} import cde.{Parameters, Field}
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], beatBytes: Int = 4) extends LazyModule class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
{ {
val node = TLManagerNode(beatBytes, TLManagerParameters( val node = TLManagerNode(beatBytes, TLManagerParameters(
address = List(AddressSet(base, size-1)), address = List(AddressSet(base, size-1)),
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes), supportsGet = TransferSizes(1, beatBytes),
fifoId = Some(0))) fifoId = Some(0)))