From e723a3f42bc47e53c41f2ae1ad22c9d68d9c8427 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 7 Sep 2017 16:01:42 -0700
Subject: [PATCH] MemoryBus: fanout the A for performance

---
 src/main/scala/coreplex/MemoryBus.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/coreplex/MemoryBus.scala b/src/main/scala/coreplex/MemoryBus.scala
index 277b54c3..336bc529 100644
--- a/src/main/scala/coreplex/MemoryBus.scala
+++ b/src/main/scala/coreplex/MemoryBus.scala
@@ -67,7 +67,7 @@ trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBu
     val mbus = new MemoryBus(mbusParams)
     for (bank <- 0 until nBanksPerChannel) {
       val offset = (bank * nMemoryChannels) + channel
-      in := sbus.toMemoryBus
+      ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus }
       mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * blockBytes, mask)))(out)
     }
     mbus