riscv/rocket-chip
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make sure merged no-alloc put still allocs if original put allocs

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This commit is contained in:
Howard Mao 2016-06-14 17:33:12 -07:00
parent 7e43b1d889
commit e716661637
2 changed files with 11 additions and 4 deletions
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9
uncore/src/main/scala/cache.scala
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@ -824,7 +824,9 @@ class CacheAcquireTracker(trackerId: Int)(implicit p: Parameters)
// First, take care of accpeting new acquires or secondary misses // First, take care of accpeting new acquires or secondary misses
// Handling of primary and secondary misses' data and write mask merging // Handling of primary and secondary misses' data and write mask merging
def iacq_can_merge = acquiresAreMergeable(io.iacq()) && def iacq_can_merge = acquiresAreMergeable(io.iacq()) &&
state =/= s_idle && state =/= s_meta_write && state =/= s_idle &&
state =/= s_meta_resp &&
state =/= s_meta_write &&
!all_pending_done && !all_pending_done &&
!io.inner.release.fire() && !io.inner.release.fire() &&
!io.outer.grant.fire() && !io.outer.grant.fire() &&
@ -919,11 +921,14 @@ class CacheAcquireTracker(trackerId: Int)(implicit p: Parameters)
add_pending_bit = addPendingBitWhenBeatNeedsRead(io.inner.acquire, Bool(alwaysWriteFullBeat)), add_pending_bit = addPendingBitWhenBeatNeedsRead(io.inner.acquire, Bool(alwaysWriteFullBeat)),
block_pending_read = ognt_counter.pending) block_pending_read = ognt_counter.pending)
// No override for first accepted acquire
val alloc_override = xact_allocate && (state =/= s_idle)
// Do write // Do write
// We write data to the cache at this level if it was Put here with allocate flag, // We write data to the cache at this level if it was Put here with allocate flag,
// written back dirty, or refilled from outer memory. // written back dirty, or refilled from outer memory.
writeDataArray( writeDataArray(
add_pending_bit = (addPendingBitWhenBeatHasDataAndAllocs(io.inner.acquire) | add_pending_bit = (addPendingBitWhenBeatHasDataAndAllocs(io.inner.acquire, alloc_override) |
addPendingBitWhenBeatHasData(io.inner.release) | addPendingBitWhenBeatHasData(io.inner.release) |
addPendingBitWhenBeatHasData(io.outer.grant, xact_allocate)), addPendingBitWhenBeatHasData(io.outer.grant, xact_allocate)),
block_pending_write = (ognt_counter.pending || block_pending_write = (ognt_counter.pending ||

6
uncore/src/main/scala/trackers.scala
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@ -79,8 +79,10 @@ trait HasPendingBitHelpers extends HasDataBeatCounters {
def addPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T], inc: Bool = Bool(true)): UInt = def addPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T], inc: Bool = Bool(true)): UInt =
addPendingBitWhenBeat(in.fire() && in.bits.hasData() && inc, in.bits) addPendingBitWhenBeat(in.fire() && in.bits.hasData() && inc, in.bits)
def addPendingBitWhenBeatHasDataAndAllocs(in: DecoupledIO[AcquireFromSrc]): UInt = def addPendingBitWhenBeatHasDataAndAllocs(
addPendingBitWhenBeatHasData(in, in.bits.allocate()) in: DecoupledIO[AcquireFromSrc],
alloc_override: Bool = Bool(false)): UInt =
addPendingBitWhenBeatHasData(in, in.bits.allocate() || alloc_override)
def addPendingBitWhenBeatNeedsRead(in: DecoupledIO[AcquireFromSrc], inc: Bool = Bool(true)): UInt = { def addPendingBitWhenBeatNeedsRead(in: DecoupledIO[AcquireFromSrc], inc: Bool = Bool(true)): UInt = {
val a = in.bits val a = in.bits