riscv/rocket-chip
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Expose carry-out bits from WideCounter

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This commit is contained in:
Andrew Waterman 2016-09-19 15:54:17 -07:00
parent f0debb89e4
commit e6c1bcfedd
1 changed files with 8 additions and 1 deletions
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9
src/main/scala/rocket/util.scala
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@ -137,11 +137,18 @@ case class WideCounter(width: Int, inc: UInt = UInt(1), reset: Boolean = true)
private val large = if (isWide) {
val r = if (reset) Reg(init=UInt(0, width - smallWidth)) else Reg(UInt(width = width - smallWidth))
when (nextSmall(smallWidth)) { r := r + UInt(1) }
when (nextSmall(smallWidth)) { r := r +& UInt(1) }
r
} else null
val value = if (isWide) Cat(large, small) else small
lazy val carryOut = {
val lo = (small ^ nextSmall) >> 1
if (!isWide) lo else {
val hi = Mux(nextSmall(smallWidth), large ^ (large +& UInt(1)), UInt(0)) >> 1
Cat(hi, lo)
}
}
def := (x: UInt) = {
small := x