diff --git a/src/main/scala/uncore/Builder.scala b/src/main/scala/uncore/Builder.scala
index 1ccbb9af..562315d9 100644
--- a/src/main/scala/uncore/Builder.scala
+++ b/src/main/scala/uncore/Builder.scala
@@ -29,7 +29,6 @@ object UncoreBuilder extends App {
   chiselMain.run(args.drop(2), gen)
 
   val pdFile = new java.io.FileWriter(s"${Driver.targetDir}/$topModuleName.prm")
-  pdFile.write(ParameterDump.getDump)
   pdFile.close
 
 }
diff --git a/src/main/scala/util/GeneratorUtils.scala b/src/main/scala/util/GeneratorUtils.scala
index 8d607560..1d76f07a 100644
--- a/src/main/scala/util/GeneratorUtils.scala
+++ b/src/main/scala/util/GeneratorUtils.scala
@@ -105,7 +105,7 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
 
   /** Output a global Parameter dump, which an external script can turn into Verilog headers. */
   def generateParameterDump {
-    writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
+    writeOutputFile(td, s"$longName.prm", "")
   }
 
   /** Output a global ConfigString, for use by the RISC-V software ecosystem. */