From e5de170215c5ee41f9e1421fc83254d4f8957a7a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 12 Feb 2014 14:28:43 -0800 Subject: [PATCH] Update Chisel, fixing Verilog backend --- chisel | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel b/chisel index f6bee8a4..0bbe5010 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit f6bee8a4d930b613262addac8af91ed57ab1c329 +Subproject commit 0bbe5010d877c0dd7cf36c54fcc141ba17dda62f