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tilelink2: split isolation gates by direction

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This commit is contained in:
Wesley W. Terpstra 2016-10-06 23:06:02 -07:00 committed by Megan Wachs
parent ad618fd55d
commit e5ac0f717f
1 changed files with 29 additions and 25 deletions
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48
src/main/scala/uncore/tilelink2/Isolation.scala
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@ -6,7 +6,7 @@ import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import diplomacy._
class TLIsolation(f: (Bool, UInt) => UInt) extends LazyModule
class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt) extends LazyModule
{
val node = TLAsyncIdentityNode()
@ -14,30 +14,32 @@ class TLIsolation(f: (Bool, UInt) => UInt) extends LazyModule
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
val iso = Bool(INPUT)
val iso_out = Bool(INPUT) // Isolate from client to manager
val iso_in = Bool(INPUT) // Isolate from manager to client
}
def ISO[T <: Data](x: T): T = x.fromBits(f(io.iso, x.asUInt))
def ISOo[T <: Data](x: T): T = x.fromBits(fOut(io.iso_out, x.asUInt))
def ISOi[T <: Data](x: T): T = x.fromBits(fIn (io.iso_in, x.asUInt))
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
out.a.mem := ISO(in.a.mem)
out.a.widx := ISO(in.a.widx)
in.a.ridx := ISO(out.a.ridx)
out.d.ridx := ISO(in.d.ridx)
in.d.widx := ISO(out.d.widx)
in.d.mem := ISO(out.d.mem)
out.a.mem := ISOo(in .a.mem)
out.a.widx := ISOo(in .a.widx)
in .a.ridx := ISOi(out.a.ridx)
out.d.ridx := ISOo(in .d.ridx)
in .d.widx := ISOi(out.d.widx)
in .d.mem := ISOi(out.d.mem)
if (edgeOut.manager.base.anySupportAcquire && edgeOut.client.base.anySupportProbe) {
in.b.widx := ISO(out.b.widx)
in.c.ridx := ISO(out.c.ridx)
in.e.ridx := ISO(out.e.ridx)
out.b.ridx := ISO(in.b.ridx)
out.c.widx := ISO(in.c.widx)
out.e.widx := ISO(in.e.widx)
in.b.mem := ISO(out.b.mem)
out.c.mem := ISO(in.c.mem)
out.e.mem := ISO(in.e.mem)
in .b.widx := ISOi(out.b.widx)
in .c.ridx := ISOi(out.c.ridx)
in .e.ridx := ISOi(out.e.ridx)
out.b.ridx := ISOo(in .b.ridx)
out.c.widx := ISOo(in .c.widx)
out.e.widx := ISOo(in .e.widx)
in .b.mem := ISOi(out.b.mem)
out.c.mem := ISOo(in .c.mem)
out.e.mem := ISOo(in .e.mem)
} else {
in .b.widx := UInt(0)
in .c.ridx := UInt(0)
@ -52,11 +54,13 @@ class TLIsolation(f: (Bool, UInt) => UInt) extends LazyModule
object TLIsolation
{
// applied to the TL source node; y.node := TLIsolation()(x.node)
// applied to the TL source node; y.node := TLIsolation(fOut, fIn)(x.node)
// f should insert an isolation gate between the input UInt and its result
def apply(f: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => Bool) = {
val iso = LazyModule(new TLIsolation(f))
// fOut is applied for data flowing from client to manager
// fIn is applied for data flowing from manager to client
def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = {
val iso = LazyModule(new TLIsolation(fOut, fIn))
iso.node := x
(iso.node, () => iso.module.io.iso)
(iso.node, () => (iso.module.io.iso_out, iso.module.io.iso_in))
}
}