riscv/rocket-chip
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This commit is contained in:
Rimas Avizienis
2011-11-10 17:41:22 -08:00
parent f86d5b1334
commit e4fa94aa27
6 changed files with 66 additions and 47 deletions
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16
rocket/src/main/scala/dpath_util.scala
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@ -135,15 +135,15 @@ class rocketDpathPCR extends Component
when (!io.exception && !io.eret && io.w.en) {
when (io.w.addr === PCR_STATUS) {
reg_status_vm <== io.w.data(16).toBool;
reg_status_vm <== io.w.data(SR_VM).toBool;
reg_status_im <== io.w.data(15,8);
reg_status_sx <== io.w.data(7).toBool;
reg_status_ux <== io.w.data(6).toBool;
reg_status_s <== io.w.data(5).toBool;
reg_status_ps <== io.w.data(4).toBool;
reg_status_ev <== HAVE_VEC && io.w.data(2).toBool;
reg_status_ef <== HAVE_FPU && io.w.data(1).toBool;
reg_status_et <== io.w.data(0).toBool;
reg_status_sx <== io.w.data(SR_SX).toBool;
reg_status_ux <== io.w.data(SR_UX).toBool;
reg_status_s <== io.w.data(SR_S).toBool;
reg_status_ps <== io.w.data(SR_PS).toBool;
reg_status_ev <== HAVE_VEC && io.w.data(SR_EV).toBool;
reg_status_ef <== HAVE_FPU && io.w.data(SR_EF).toBool;
reg_status_et <== io.w.data(SR_ET).toBool;
}
when (io.w.addr === PCR_EPC) { reg_epc <== io.w.data(VADDR_BITS-1,0).toUFix; }
when (io.w.addr === PCR_BADVADDR) { reg_badvaddr <== io.w.data(VADDR_BITS-1,0).toUFix; }