riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

use Mem to implement queues to speed things up

Browse Source
This commit is contained in:
Andrew Waterman
2012-07-13 21:48:05 -07:00
parent fd95159837
commit e496cd7584
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/queues.scala
View File

@@ -54,7 +54,7 @@ class queue[T <: Data](val entries: Int, pipe: Boolean = false, flushable: Boole
} }
} }
val ram = Vec(entries) { Reg() { data } } val ram = Mem(entries) { data }
when (do_enq) { ram(enq_ptr) := io.enq.bits } when (do_enq) { ram(enq_ptr) := io.enq.bits }
val ptr_match = enq_ptr === deq_ptr val ptr_match = enq_ptr === deq_ptr