riscv/rocket-chip
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use Mem to implement queues to speed things up

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This commit is contained in:
Andrew Waterman 2012-07-13 21:48:05 -07:00
parent fd95159837
commit e496cd7584
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/queues.scala
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@ -54,7 +54,7 @@ class queue[T <: Data](val entries: Int, pipe: Boolean = false, flushable: Boole
} }
} }
val ram = Vec(entries) { Reg() { data } } val ram = Mem(entries) { data }
when (do_enq) { ram(enq_ptr) := io.enq.bits } when (do_enq) { ram(enq_ptr) := io.enq.bits }
val ptr_match = enq_ptr === deq_ptr val ptr_match = enq_ptr === deq_ptr