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tile: remove PAddrBits in favor of SharedMemoryTLEdge

This commit is contained in:
Henry Cook 2017-08-31 18:48:59 -07:00
parent e7de7f3e82
commit e46aeb7342
9 changed files with 16 additions and 16 deletions

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@ -5,7 +5,6 @@ package freechips.rocketchip.coreplex
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.PAddrBits
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._

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@ -15,11 +15,10 @@ import freechips.rocketchip.util._
class BaseCoreplexConfig extends Config ((site, here, up) => {
// Tile parameters
case PAddrBits => 32
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
case ASIdBits => 0
case XLen => 64 // Applies to all cores
case ResetVectorBits => site(PAddrBits)
case ResetVectorBits => 32 // TODO: site(SharedMemoryTLEdge).bundle.addressBits
case MaxHartIdBits => log2Up(site(RocketTilesKey).size)
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketTilesKey => Nil // Will be added by partial configs found below

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@ -6,7 +6,7 @@ package freechips.rocketchip.groundtest
import Chisel._
import freechips.rocketchip.config.Config
import freechips.rocketchip.coreplex._
import freechips.rocketchip.rocket.{DCacheParams, PAddrBits}
import freechips.rocketchip.rocket.{DCacheParams}
import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
/** Actual testing target Configs */
@ -21,7 +21,7 @@ class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config(
case GroundTestTilesKey => params.map { dcp => TraceGenParams(
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = site(PAddrBits),
addrBits = 32,
addrBag = {
val nSets = 2
val nWays = 1

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@ -97,15 +97,18 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
}
/** Mix-ins for constructing tiles that have optional scratchpads */
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCoreParameters {
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
val module: CanHaveScratchpadModule
val xLenBytes = p(XLen)/8
val cacheBlockBytes = p(CacheBlockBytes)
val fetchBytes = tileParams.core.fetchBytes
val slaveNode = TLInputNode() // Up to two uses for this input node:
// 1) Frontend always exists, but may or may not have a scratchpad node
// 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), earlyAck=true))
val ww = LazyModule(new TLWidthWidget(xLen/8))
val fg = LazyModule(new TLFragmenter(fetchBytes, cacheBlockBytes, earlyAck=true))
val ww = LazyModule(new TLWidthWidget(xLenBytes))
val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
@ -113,7 +116,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
frontend.slaveNode :*= fg.node
fg.node :*= ww.node
ww.node :*= slaveNode
scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) }
scratch foreach { lm => lm.node := TLFragmenter(xLenBytes, cacheBlockBytes, earlyAck=true)(slaveNode) }
}
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>

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@ -13,7 +13,6 @@ import freechips.rocketchip.tile.{XLen, CoreModule, CoreBundle}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
case object PAddrBits extends Field[Int]
case object PgLevels extends Field[Int]
case object ASIdBits extends Field[Int]

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@ -34,6 +34,7 @@ trait HasTileParameters {
val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
val usingPTW = usingVM
val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
val hartIdLen = p(MaxHartIdBits)
def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size

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@ -27,6 +27,9 @@ trait CoreParams {
val nLocalInterrupts: Int
val nL2TLBEntries: Int
val jumpInFrontend: Boolean
def instBytes: Int = instBits / 8
def fetchBytes: Int = fetchWidth * instBytes
}
trait HasCoreParameters extends HasTileParameters {
@ -56,14 +59,14 @@ trait HasCoreParameters extends HasTileParameters {
def pgIdxBits = 12
def pgLevelBits = 10 - log2Ceil(xLen / 32)
def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
val paddrBits = p(PAddrBits)
def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits
def ppnBits = paddrBits - pgIdxBits
def vpnBits = vaddrBits - pgIdxBits
val pgLevels = p(PgLevels)
val asIdBits = p(ASIdBits)
val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
def coreMaxAddrBits = paddrBits max vaddrBitsExtended
val maxPAddrBits = xLen match { case 32 => 34; case 64 => 56 }
require(paddrBits <= maxPAddrBits)

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@ -6,7 +6,6 @@ import Chisel._
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.rocket.PAddrBits
import freechips.rocketchip.tilelink.ClientMetadata
import freechips.rocketchip.util._

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@ -136,9 +136,6 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
with HasLazyRoCCModule
with CanHaveScratchpadModule {
require(outer.p(PAddrBits) == outer.masterNode.edgesIn(0).bundle.addressBits,
s"outer.p(PAddrBits) (${outer.p(PAddrBits)}) must be == outer.masterNode.addressBits (${outer.masterNode.edgesIn(0).bundle.addressBits})")
val core = Module(p(BuildCore)(outer.p))
decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
core.io.hartid := io.hartid // Pass through the hartid