riscv/rocket-chip
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tile: remove PAddrBits in favor of SharedMemoryTLEdge

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This commit is contained in:
Henry Cook
2017-08-31 18:48:59 -07:00
parent e7de7f3e82
commit e46aeb7342
9 changed files with 16 additions and 16 deletions
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3
src/main/scala/tile/RocketTile.scala
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@ -136,9 +136,6 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
with HasLazyRoCCModule
with CanHaveScratchpadModule {
require(outer.p(PAddrBits) == outer.masterNode.edgesIn(0).bundle.addressBits,
s"outer.p(PAddrBits) (${outer.p(PAddrBits)}) must be == outer.masterNode.addressBits (${outer.masterNode.edgesIn(0).bundle.addressBits})")
val core = Module(p(BuildCore)(outer.p))
decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
core.io.hartid := io.hartid // Pass through the hartid