riscv/rocket-chip
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tile: remove PAddrBits in favor of SharedMemoryTLEdge

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Henry Cook
2017-08-31 18:48:59 -07:00
parent e7de7f3e82
commit e46aeb7342
9 changed files with 16 additions and 16 deletions
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src/main/scala/tile/L1Cache.scala
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@ -6,7 +6,6 @@ import Chisel._
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.rocket.PAddrBits
import freechips.rocketchip.tilelink.ClientMetadata
import freechips.rocketchip.util._