tile: remove PAddrBits in favor of SharedMemoryTLEdge

src/main/scala/tile/BaseTile.scala

@@ -34,6 +34,7 @@ trait HasTileParameters {
   val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
   val usingPTW = usingVM
   val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
+
   val hartIdLen = p(MaxHartIdBits)
 
   def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size

src/main/scala/tile/Core.scala

@@ -27,6 +27,9 @@ trait CoreParams {
   val nLocalInterrupts: Int
   val nL2TLBEntries: Int
   val jumpInFrontend: Boolean
+
+  def instBytes: Int = instBits / 8
+  def fetchBytes: Int = fetchWidth * instBytes
 }
 
 trait HasCoreParameters extends HasTileParameters {
@@ -56,14 +59,14 @@ trait HasCoreParameters extends HasTileParameters {
   def pgIdxBits = 12
   def pgLevelBits = 10 - log2Ceil(xLen / 32)
   def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
-  val paddrBits = p(PAddrBits)
+  def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits
   def ppnBits = paddrBits - pgIdxBits
   def vpnBits = vaddrBits - pgIdxBits
   val pgLevels = p(PgLevels)
   val asIdBits = p(ASIdBits)
   val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
   val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
-  val coreMaxAddrBits = paddrBits max vaddrBitsExtended
+  def coreMaxAddrBits = paddrBits max vaddrBitsExtended
   val maxPAddrBits = xLen match { case 32 => 34; case 64 => 56 }
   require(paddrBits <= maxPAddrBits)
 

src/main/scala/tile/L1Cache.scala

@@ -6,7 +6,6 @@ import Chisel._
 
 import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.coreplex.CacheBlockBytes
-import freechips.rocketchip.rocket.PAddrBits
 import freechips.rocketchip.tilelink.ClientMetadata
 import freechips.rocketchip.util._
 

src/main/scala/tile/RocketTile.scala

@@ -136,9 +136,6 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
     with HasLazyRoCCModule
     with CanHaveScratchpadModule {
 
-  require(outer.p(PAddrBits) == outer.masterNode.edgesIn(0).bundle.addressBits,
-    s"outer.p(PAddrBits) (${outer.p(PAddrBits)}) must be == outer.masterNode.addressBits (${outer.masterNode.edgesIn(0).bundle.addressBits})")
-
   val core = Module(p(BuildCore)(outer.p))
   decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
   core.io.hartid := io.hartid // Pass through the hartid