riscv/rocket-chip
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tile: remove PAddrBits in favor of SharedMemoryTLEdge

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This commit is contained in:
Henry Cook
2017-08-31 18:48:59 -07:00
parent e7de7f3e82
commit e46aeb7342
9 changed files with 16 additions and 16 deletions
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4
src/main/scala/groundtest/Configs.scala
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@ -6,7 +6,7 @@ package freechips.rocketchip.groundtest
import Chisel._
import freechips.rocketchip.config.Config
import freechips.rocketchip.coreplex._
import freechips.rocketchip.rocket.{DCacheParams, PAddrBits}
import freechips.rocketchip.rocket.{DCacheParams}
import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
/** Actual testing target Configs */
@ -21,7 +21,7 @@ class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config(
case GroundTestTilesKey => params.map { dcp => TraceGenParams(
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = site(PAddrBits),
addrBits = 32,
addrBag = {
val nSets = 2
val nWays = 1