riscv/rocket-chip
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tile: remove PAddrBits in favor of SharedMemoryTLEdge

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This commit is contained in:
Henry Cook
2017-08-31 18:48:59 -07:00
parent e7de7f3e82
commit e46aeb7342
9 changed files with 16 additions and 16 deletions
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1
src/main/scala/coreplex/BaseCoreplex.scala
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@ -5,7 +5,6 @@ package freechips.rocketchip.coreplex
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.PAddrBits
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._

3
src/main/scala/coreplex/Configs.scala
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@ -15,11 +15,10 @@ import freechips.rocketchip.util._
class BaseCoreplexConfig extends Config ((site, here, up) => {
// Tile parameters
case PAddrBits => 32
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
case ASIdBits => 0
case XLen => 64 // Applies to all cores
case ResetVectorBits => site(PAddrBits)
case ResetVectorBits => 32 // TODO: site(SharedMemoryTLEdge).bundle.addressBits
case MaxHartIdBits => log2Up(site(RocketTilesKey).size)
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketTilesKey => Nil // Will be added by partial configs found below