riscv/rocket-chip
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Fix compile error and eliminate wasteful wires

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Wesley W. Terpstra 2017-06-30 01:06:02 -07:00 committed by GitHub
parent 834bcf6b7e
commit e43b7accf9
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/uncore/devices/Plic.scala
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@ -176,11 +176,11 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
PLICConsts.enableBase(i) -> e.map(b => RegField(1, b)) PLICConsts.enableBase(i) -> e.map(b => RegField(1, b))
} }
val claimer = Wire(init = Vec.fill(nHarts){Bool(false)}) val claimer = Wire(Vec(nHarts, Bool()))
val claiming = Wire(init = Vec.tabulate(nHarts){i => Mux(claimer(i), UIntToOH(maxDevs(i)), UInt(0))}) val claiming = Vec.tabulate(nHarts){i => Mux(claimer(i), UIntToOH(maxDevs(i), nDevices+1), UInt(0))}
val claimedDevs = Wire(init = Vec(claiming.reduceLeft( _ | _ ).toBools)) val claimedDevs = Vec(claiming.reduceLeft( _ | _ ).toBools)
for ((p, g), c) <- (pending zip gateways) zip claimedDevs) { (pending zip gateways) zip claimedDevs) foreach { case ((p, g), c) =>
g.ready := !p g.ready := !p
g.complete := false g.complete := false
when(c) { when(c) {