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tilelink2: track interrupt connectivity like in TL2

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This commit is contained in:
Wesley W. Terpstra
2016-09-17 13:56:35 -07:00
parent fd3ac4653c
commit e437508548
2 changed files with 26 additions and 8 deletions
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src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@ -75,7 +75,7 @@ object TLRegisterNode
abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Option[Int], beatBytes: Int, undefZero: Boolean) extends LazyModule
{
val node = TLRegisterNode(address, concurrency, beatBytes, undefZero)
val intnode = IntSourceNode(name + s" @ ${address.base}", interrupts)
val intnode = IntSourceNode(interrupts)
}
case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])