From e3c7bb3b1fbb46e5eff2322c9e618b45ec0b22e0 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 29 Jun 2017 19:07:12 -0700 Subject: [PATCH] SRAM: MemoryDevices use .reg (not .reg("mem")) (#835) --- src/main/scala/uncore/tilelink2/SRAM.scala | 6 ++++-- src/main/scala/uncore/tilelink2/TestRAM.scala | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala index 136f4047..3e7c2b75 100644 --- a/src/main/scala/uncore/tilelink2/SRAM.scala +++ b/src/main/scala/uncore/tilelink2/SRAM.scala @@ -10,11 +10,13 @@ import util._ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule { - val device = name.map(new SimpleDevice(_, Seq("sifive,sram0"))).getOrElse(new MemoryDevice) + private val resources = + name.map(new SimpleDevice(_, Seq("sifive,sram0")).reg("mem")).getOrElse(new MemoryDevice().reg) + val node = TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = List(address), - resources = device.reg("mem"), + resources = resources, regionType = RegionType.UNCACHED, executable = executable, supportsGet = TransferSizes(1, beatBytes), diff --git a/src/main/scala/uncore/tilelink2/TestRAM.scala b/src/main/scala/uncore/tilelink2/TestRAM.scala index 98426201..c1b28f56 100644 --- a/src/main/scala/uncore/tilelink2/TestRAM.scala +++ b/src/main/scala/uncore/tilelink2/TestRAM.scala @@ -15,7 +15,7 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int val node = TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = List(address), - resources = device.reg("mem"), + resources = device.reg, regionType = RegionType.UNCACHED, executable = executable, supportsGet = TransferSizes(1, beatBytes),