riscv/rocket-chip
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Refactor breakpoints and support range comparison (currently disabled)

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This commit is contained in:
Andrew Waterman
2016-06-10 19:55:58 -07:00
parent c8c7246cce
commit e3b4b55836
3 changed files with 53 additions and 32 deletions
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3
rocket/src/main/scala/rocket.scala
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@ -228,8 +228,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
val bpu = Module(new BreakpointUnit)
bpu.io.status := csr.io.status
bpu.io.bpcontrol := csr.io.bpcontrol
bpu.io.bpaddress := csr.io.bpaddress
bpu.io.bp := csr.io.bp
bpu.io.pc := id_pc
bpu.io.ea := mem_reg_wdata