riscv/rocket-chip
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set invalidate_lr in other rocc examples (#47)

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This should fix https://travis-ci.org/ucb-bar/rocket-chip/jobs/137607305
This commit is contained in:
Colin Schmidt 2016-06-14 16:59:37 -07:00 committed by Andrew Waterman
parent e3b4b55836
commit e3816d5fc7
1 changed files with 2 additions and 0 deletions
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rocket/src/main/scala/rocc.scala
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@ -178,6 +178,7 @@ class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
io.busy := (state =/= s_idle) io.busy := (state =/= s_idle)
io.interrupt := Bool(false) io.interrupt := Bool(false)
io.mem.req.valid := Bool(false) io.mem.req.valid := Bool(false)
io.mem.invalidate_lr := Bool(false)
io.autl.acquire.valid := Bool(false) io.autl.acquire.valid := Bool(false)
io.autl.grant.ready := Bool(false) io.autl.grant.ready := Bool(false)
} }
@ -259,6 +260,7 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
io.busy := (state =/= s_idle) io.busy := (state =/= s_idle)
io.interrupt := Bool(false) io.interrupt := Bool(false)
io.mem.req.valid := Bool(false) io.mem.req.valid := Bool(false)
io.mem.invalidate_lr := Bool(false)
} }
class OpcodeSet(val opcodes: Seq[UInt]) { class OpcodeSet(val opcodes: Seq[UInt]) {