fix coherence bug
popping wrong store dependence queue
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77c405ffa1
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@ -295,8 +295,9 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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when(req_cmd.ready && req_cmd.valid) {
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when(req_cmd.ready && req_cmd.valid) {
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cmd_sent := Bool(true)
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cmd_sent := Bool(true)
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}
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}
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when(req_data.ready && req_data.valid) {
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when(req_data.ready && at_front_of_dep_queue) {
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pop_data := UFix(1) << tile_id
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pop_data := UFix(1) << tile_id
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when (data.valid) {
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mem_cnt := mem_cnt_next
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mem_cnt := mem_cnt_next
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when(mem_cnt_next === UFix(0)) {
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when(mem_cnt_next === UFix(0)) {
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pop_dep := UFix(1) << tile_id
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pop_dep := UFix(1) << tile_id
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@ -304,6 +305,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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}
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}
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}
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}
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}
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}
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}
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def doMemReqRead(req_cmd: ioDecoupled[MemReqCmd], trigger: Bool) {
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def doMemReqRead(req_cmd: ioDecoupled[MemReqCmd], trigger: Bool) {
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req_cmd.valid := Bool(true)
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req_cmd.valid := Bool(true)
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@ -391,7 +393,6 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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io.pop_p_rep := io.p_rep_cnt_dec
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io.pop_p_rep := io.p_rep_cnt_dec
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if(ntiles > 1) p_rep_count := p_rep_count - dec
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if(ntiles > 1) p_rep_count := p_rep_count - dec
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when(p_rep_count === dec) {
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when(p_rep_count === dec) {
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io.pop_p_rep := Bool(true)
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state := s_mem
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state := s_mem
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}
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}
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}
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}
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