riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

use correct parameters object for MMIO width adapter

Browse Source
This commit is contained in:
Howard Mao
2016-09-27 11:13:07 -07:00
committed by Henry Cook
parent 201e247f73
commit e36441a046
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocketchip/Periphery.scala
View File

@ -213,7 +213,7 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
val pBus: TileLinkRecursiveInterconnect val pBus: TileLinkRecursiveInterconnect
val mmio_ports = p(ExtMMIOPorts) map { port => val mmio_ports = p(ExtMMIOPorts) map { port =>
TileLinkWidthAdapter(pBus.port(port.name), outerMMIOParams) TileLinkWidthAdapter(pBus.port(port.name), outermostMMIOParams)
} }
val mmio_axi_start = 0 val mmio_axi_start = 0