riscv/rocket-chip
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use correct parameters object for MMIO width adapter

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Howard Mao authored and Henry Cook committed 2016-09-27 12:48:01 -07:00
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commit e36441a046
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src/main/scala/rocketchip/Periphery.scala
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@@ -213,7 +213,7 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
val pBus: TileLinkRecursiveInterconnect val pBus: TileLinkRecursiveInterconnect
val mmio_ports = p(ExtMMIOPorts) map { port => val mmio_ports = p(ExtMMIOPorts) map { port =>
TileLinkWidthAdapter(pBus.port(port.name), outerMMIOParams) TileLinkWidthAdapter(pBus.port(port.name), outermostMMIOParams)
} }
val mmio_axi_start = 0 val mmio_axi_start = 0