From e346f21725e3de2ac2939db11e644f29e9e3ac3b Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Fri, 3 Aug 2012 18:59:37 -0700
Subject: [PATCH] fix control bug in LLC

structural hazard on tag ram caused deadlock
---
 uncore/llc.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/uncore/llc.scala b/uncore/llc.scala
index 546da774..eece03ed 100644
--- a/uncore/llc.scala
+++ b/uncore/llc.scala
@@ -154,13 +154,14 @@ class LLCMSHRFile(sets: Int, ways: Int, outstanding: Int) extends Component
   val conflicts = Cat(Bits(0), (0 until outstanding).map(i => valid(i) && io.cpu.bits.addr(log2Up(sets)-1, 0) === mshr(i).addr(log2Up(sets)-1, 0)):_*)
   io.cpu.ready := !conflicts.orR && !validBits.andR
 
-  io.data.valid := replay && io.tag.ready || writeback
+  io.data.valid := writeback
   io.data.bits.rw := Bool(false)
   io.data.bits.tag := mshr(replayId).tag
   io.data.bits.isWriteback := Bool(true)
   io.data.bits.addr := Cat(mshr(writebackId).old_tag, mshr(writebackId).addr(log2Up(sets)-1, 0)).toUFix
   io.data.bits.way := mshr(writebackId).way
   when (replay) {
+    io.data.valid := io.tag.ready
     io.data.bits.isWriteback := Bool(false)
     io.data.bits.addr := mshr(replayId).addr
     io.data.bits.way := mshr(replayId).way