From e33648532b085d52b98ed26393a403602cd707a8 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 15 Jan 2013 15:57:06 -0800 Subject: [PATCH] Refactored packet headers/payloads --- riscv-rocket | 2 +- src/main/scala/RocketChip.scala | 122 ++++++++++++++++++-------------- src/main/scala/fpga.scala | 49 ++++++++----- uncore | 2 +- 4 files changed, 100 insertions(+), 75 deletions(-) diff --git a/riscv-rocket b/riscv-rocket index f6548d6c..2dda8064 160000 --- a/riscv-rocket +++ b/riscv-rocket @@ -1 +1 @@ -Subproject commit f6548d6cb5ff1b62077e8fd52ab9834fdabd8037 +Subproject commit 2dda8064a3e102e364f337b56eb98bf93a0c67bb diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index c54a586b..1b1348ef 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -10,82 +10,82 @@ import scala.collection.mutable.HashMap object TileToCrossbarShim { - def apply[T <: Data](logIO: TileIO[T])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = { - val shim = (new TileToCrossbarShim) { logIO.bits.clone } + def apply[T <: Data](logIO: ClientSourcedIO[LogicalNetworkIO[T]])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = { + val shim = (new TileToCrossbarShim) { logIO.bits.payload.clone } shim.io.in <> logIO shim.io.out } } class TileToCrossbarShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) extends Component { val io = new Bundle { - val in = (new TileIO){ data }.flip - val out = (new BasicCrossbarIO){ data } + val in = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}.flip + val out = (new FIFOIO){(new BasicCrossbarIO){ data }} } - io.out.header.src := io.in.header.src + UFix(lconf.nHubs) - io.out.header.dst := io.in.header.dst - io.out.bits := io.in.bits + io.out.bits.header.src := io.in.bits.header.src + UFix(lconf.nHubs) + io.out.bits.header.dst := io.in.bits.header.dst + io.out.bits.payload := io.in.bits.payload io.out.valid := io.in.valid io.in.ready := io.out.ready } object HubToCrossbarShim { - def apply[T <: Data](logIO: HubIO[T])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = { - val shim = (new HubToCrossbarShim) { logIO.bits.clone } + def apply[T <: Data](logIO: MasterSourcedIO[LogicalNetworkIO[T]])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = { + val shim = (new HubToCrossbarShim) { logIO.bits.payload.clone } shim.io.in <> logIO shim.io.out } } class HubToCrossbarShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) extends Component { val io = new Bundle { - val in = (new HubIO){ data } - val out = (new BasicCrossbarIO){ data } + val in = (new MasterSourcedIO){(new LogicalNetworkIO){ data }} + val out = (new FIFOIO){(new BasicCrossbarIO){ data }} } - io.out.header.src := io.in.header.src - io.out.header.dst := io.in.header.dst + UFix(lconf.nHubs) - io.out.bits := io.in.bits + io.out.bits.header.src := io.in.bits.header.src + io.out.bits.header.dst := io.in.bits.header.dst + UFix(lconf.nHubs) + io.out.bits.payload := io.in.bits.payload io.out.valid := io.in.valid io.in.ready := io.out.ready } object CrossbarToTileShim { - def apply[T <: Data](physIO: BasicCrossbarIO[T])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = { - val shim = (new CrossbarToTileShim) { physIO.bits.clone } + def apply[T <: Data](physIO: FIFOIO[BasicCrossbarIO[T]])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = { + val shim = (new CrossbarToTileShim) { physIO.bits.payload.clone } shim.io.in <> physIO shim.io.out } } class CrossbarToTileShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) extends Component { val io = new Bundle { - val in = (new BasicCrossbarIO){ data }.flip - val out = (new TileIO){ data } + val in = (new FIFOIO){(new BasicCrossbarIO){ data }}.flip + val out = (new ClientSourcedIO){(new LogicalNetworkIO){ data }} } - io.out.header.src := io.in.header.src - io.out.header.dst := io.in.header.dst - UFix(lconf.nHubs) - io.out.bits := io.in.bits + io.out.bits.header.src := io.in.bits.header.src + io.out.bits.header.dst := io.in.bits.header.dst - UFix(lconf.nHubs) + io.out.bits.payload := io.in.bits.payload io.out.valid := io.in.valid io.in.ready := io.out.ready } object CrossbarToHubShim { - def apply[T <: Data](physIO: BasicCrossbarIO[T])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = { - val shim = (new CrossbarToHubShim) { physIO.bits.clone } + def apply[T <: Data](physIO: FIFOIO[BasicCrossbarIO[T]])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = { + val shim = (new CrossbarToHubShim) { physIO.bits.payload.clone } shim.io.in <> physIO shim.io.out } } class CrossbarToHubShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) extends Component { val io = new Bundle { - val in = (new BasicCrossbarIO){ data }.flip - val out = (new HubIO){ data }.flip + val in = (new FIFOIO){(new BasicCrossbarIO){ data }}.flip + val out = (new MasterSourcedIO){(new LogicalNetworkIO){ data }}.flip } - io.out.header.src := io.in.header.src - UFix(lconf.nHubs) - io.out.header.dst := io.in.header.dst - io.out.bits := io.in.bits + io.out.bits.header.src := io.in.bits.header.src - UFix(lconf.nHubs) + io.out.bits.header.dst := io.in.bits.header.dst + io.out.bits.payload := io.in.bits.payload io.out.valid := io.in.valid io.in.ready := io.out.ready } -class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgent])(implicit conf: LogicalNetworkConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf) { +class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: LogicalNetworkConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf) { type TileLinkType = TileLinkIO val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkType).flip}; case h:MasterCoherenceAgent => {new TileLinkType}})){ new TileLinkType } @@ -94,8 +94,8 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgent])(implicit conf //bundle containing LogicalNetworkIOs val tl = new TileLinkType val payloadBitsForEachPhysicalNetwork = tl.getClass.getMethods.filter( x => - classOf[LogicalNetworkIO[Data]].isAssignableFrom(x.getReturnType)).map( - _.invoke(tl).asInstanceOf[LogicalNetworkIO[Data]].bits) + classOf[DirectionalFIFOIO[Data]].isAssignableFrom(x.getReturnType)).map( + _.invoke(tl).asInstanceOf[DirectionalFIFOIO[LogicalNetworkIO[Data]]].bits.payload) implicit val pconf = new PhysicalNetworkConfiguration(conf.nEndpoints, conf.idBits)//same config for all networks val physicalNetworks: Seq[BasicCrossbar[Data]] = payloadBitsForEachPhysicalNetwork.map(d => (new BasicCrossbar){d.clone}) @@ -105,13 +105,13 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgent])(implicit conf //shims to convert headers and process flits in the process. endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => { val logNetIOSubBundles = io.getClass.getMethods.filter( x => - classOf[LogicalNetworkIO[Data]].isAssignableFrom(x.getReturnType)).zipWithIndex - val tileProducedSubBundles = logNetIOSubBundles.filter( x => // filter -> parition? - classOf[TileIO[Data]].isAssignableFrom(x._1.getReturnType)).map{ case (m,i) => - (m.invoke(io).asInstanceOf[TileIO[Data]],i) } + classOf[DirectionalFIFOIO[Data]].isAssignableFrom(x.getReturnType)).zipWithIndex + val tileProducedSubBundles = logNetIOSubBundles.filter( x => + classOf[ClientSourcedIO[Data]].isAssignableFrom(x._1.getReturnType)).map{ case (m,i) => + (m.invoke(io).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]],i) } val hubProducedSubBundles = logNetIOSubBundles.filter( x => - classOf[HubIO[Data]].isAssignableFrom(x._1.getReturnType)).map{ case (m,i) => - (m.invoke(io).asInstanceOf[HubIO[Data]],i) } + classOf[MasterSourcedIO[Data]].isAssignableFrom(x._1.getReturnType)).map{ case (m,i) => + (m.invoke(io).asInstanceOf[MasterSourcedIO[LogicalNetworkIO[Data]]],i) } end match { case x:ClientCoherenceAgent => { tileProducedSubBundles.foreach{ case (sl,i) => { @@ -376,28 +376,42 @@ class Top extends Component { tile.io.host.ipi_rep <> Queue(hl.ipi_rep) error_mode = error_mode || Reg(tile.io.host.debug.error_mode) - tl.xact_init <> Queue(tile.io.tilelink.xact_init) - tl.xact_init_data <> Queue(tile.io.tilelink.xact_init_data) + val x_init_q = Queue(tile.io.tilelink.xact_init) + tl.xact_init.valid := x_init_q.valid + tl.xact_init.bits.payload := x_init_q.bits.payload + tl.xact_init.bits.header.src := UFix(i) + tl.xact_init.bits.header.dst := UFix(0) + x_init_q.ready := tl.xact_init.ready + val x_init_data_q = Queue(tile.io.tilelink.xact_init_data) + tl.xact_init_data.valid := x_init_data_q.valid + tl.xact_init_data.bits.payload := x_init_data_q.bits.payload + tl.xact_init_data.bits.header.src := UFix(i) + tl.xact_init_data.bits.header.dst := UFix(0) + x_init_data_q.ready := tl.xact_init_data.ready + val x_finish_q = Queue(tile.io.tilelink.xact_finish) + tl.xact_finish.valid := x_finish_q.valid + tl.xact_finish.bits.payload := x_finish_q.bits.payload + tl.xact_finish.bits.header.src := UFix(i) + tl.xact_finish.bits.header.dst := UFix(0) + x_finish_q.ready := tl.xact_finish.ready + val p_rep_q = Queue(tile.io.tilelink.probe_rep, 1) + tl.probe_rep.valid := p_rep_q.valid + tl.probe_rep.bits.payload := p_rep_q.bits.payload + tl.probe_rep.bits.header.src := UFix(i) + tl.probe_rep.bits.header.dst := UFix(0) + p_rep_q.ready := tl.probe_rep.ready + val p_rep_data_q = Queue(tile.io.tilelink.probe_rep_data) + tl.probe_rep_data.valid := p_rep_data_q.valid + tl.probe_rep_data.bits.payload := p_rep_data_q.bits.payload + tl.probe_rep_data.bits.header.src := UFix(i) + tl.probe_rep_data.bits.header.dst := UFix(0) + p_rep_data_q.ready := tl.probe_rep_data.ready + tile.io.tilelink.xact_abort <> Queue(tl.xact_abort) tile.io.tilelink.xact_rep <> Queue(tl.xact_rep, 1, pipe = true) - tl.xact_finish <> Queue(tile.io.tilelink.xact_finish) tile.io.tilelink.probe_req <> Queue(tl.probe_req) - tl.probe_rep <> Queue(tile.io.tilelink.probe_rep, 1) - tl.probe_rep_data <> Queue(tile.io.tilelink.probe_rep_data) il := hl.reset - tl.xact_init.header.src := UFix(i) - tl.xact_init.header.dst := UFix(0) - tl.xact_init_data.header.src := UFix(i) - tl.xact_init_data.header.dst := UFix(0) - tl.probe_rep.header.src := UFix(i) - tl.probe_rep.header.dst := UFix(0) - tl.probe_rep_data.header.src := UFix(i) - tl.probe_rep_data.header.dst := UFix(0) - tl.xact_finish.header.src := UFix(i) - tl.xact_finish.header.dst := UFix(0) - //TODO: What about incoming headers? - } io.host <> uncore.io.host diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index e754afae..e4f24de0 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -6,23 +6,26 @@ import uncore._ import rocket._ import rocket.Constants._ -class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Component +class FPGAUncore(htif_width: Int)(implicit conf: CoherenceHubConfiguration) extends Component { val io = new Bundle { - val host = new ioHost(htif_width) + val host = new HostIO(htif_width) val mem = new ioMem - val tiles = Vec(conf.ntiles) { new ioTileLink() }.flip - val htif = Vec(conf.ntiles) { new ioHTIF(conf.ntiles) }.flip + val tiles = Vec(conf.ln.nTiles) { new TileLinkIO()(conf.ln) }.flip + val htif = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles) }.flip + val incoherent = Vec(conf.ln.nTiles) { Bool() }.asInput } val htif = new rocketHTIF(htif_width) htif.io.cpu <> io.htif io.host <> htif.io.host - val hub = new CoherenceHubBroadcast()(conf.copy(ntiles = conf.ntiles+1)) - for (i <- 0 until conf.ntiles) + val lnWithHtif = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1, nTiles = conf.ln.nTiles+1) + val hub = new CoherenceHubBroadcast()(conf.copy(ln = lnWithHtif)) + for (i <- 0 until conf.ln.nTiles) hub.io.tiles(i) <> io.tiles(i) - hub.io.tiles(conf.ntiles) <> htif.io.mem + hub.io.tiles(conf.ln.nTiles) <> htif.io.mem + hub.io.incoherent <> io.incoherent io.mem.req_cmd <> Queue(hub.io.mem.req_cmd) io.mem.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES*2) @@ -32,30 +35,37 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Co class FPGATop extends Component { val htif_width = 16 val io = new Bundle { - val debug = new ioDebug - val host = new ioHost(htif_width) + val debug = new DebugIO + val host = new HostIO(htif_width) val mem = new ioMem } val co = new MESICoherence - implicit val uconf = UncoreConfiguration(3, 3, co) + implicit val lnConf = LogicalNetworkConfiguration(4, 3, 1, 3) + implicit val uconf = CoherenceHubConfiguration(co, lnConf) val uncore = new FPGAUncore(htif_width = htif_width) + val resetSigs = Vec(uconf.ln.nTiles){ Bool() } + val ic = ICacheConfig(64, 1, co, ntlb = 4, nbtb = 4) + val dc = DCacheConfig(64, 1, co, ntlb = 4, + nmshr = 2, nrpq = 16, nsdq = 17) + val rc = RocketConfiguration(uconf.ln, co, ic, dc, + fastMulDiv = false, + fpu = false, vec = false) + val tileList = (0 until uconf.ln.nTiles).map(r => new Tile(resetSignal = resetSigs(r))(rc)) + io.debug.error_mode := Bool(false) - for (i <- 0 until uconf.ntiles) { + for (i <- 0 until uconf.ln.nTiles) { val hl = uncore.io.htif(i) val tl = uncore.io.tiles(i) + val il = uncore.io.incoherent(i) + + resetSigs(i) := hl.reset + val tile = tileList(i) - val ic = ICacheConfig(64, 1, co, ntlb = 4, nbtb = 4) - val dc = DCacheConfig(64, 1, co, ntlb = 4, - nmshr = 2, nrpq = 16, nsdq = 17) - val rc = RocketConfiguration(uconf.ntiles, co, ic, dc, - fastMulDiv = false, - fpu = false, vec = false) - val tile = new Tile(resetSignal = hl.reset)(rc) tile.io.host <> hl when (tile.io.host.debug.error_mode) { io.debug.error_mode := Bool(true) } - tl.incoherent := hl.reset + il := hl.reset tl.xact_init <> Queue(tile.io.tilelink.xact_init) tl.xact_init_data <> Queue(tile.io.tilelink.xact_init_data) tile.io.tilelink.xact_abort <> Queue(tl.xact_abort) @@ -64,6 +74,7 @@ class FPGATop extends Component { tile.io.tilelink.probe_req <> Queue(tl.probe_req) tl.probe_rep <> Queue(tile.io.tilelink.probe_rep) tl.probe_rep_data <> Queue(tile.io.tilelink.probe_rep_data) + //TODO: Set logcal network headers here } io.host <> uncore.io.host diff --git a/uncore b/uncore index c781a315..167f2675 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit c781a3152a34071f7f18afccddf59b0c16c3acee +Subproject commit 167f2675a6ef64a6c749e7b6023e10f596a6b1df