riscv/rocket-chip
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factor out global constants

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This commit is contained in:
Andrew Waterman 2012-11-06 08:18:40 -08:00
parent 1305372ce7
commit e2afae011a
3 changed files with 11 additions and 9 deletions
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12
csrc/emulator.cc
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@ -155,8 +155,8 @@ int main(int argc, char** argv)
strcpy(wb_inst_str, disasm.disassemble(insn).c_str()); strcpy(wb_inst_str, disasm.disassemble(insn).c_str());
fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \ fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \
(long long)trace_count, tile.Top_Tile_cpu_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_cpu_dpath__wb_reg_pc.lo_word(), \ (long long)trace_count, tile.Top_Tile_core_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_core_dpath__wb_reg_pc.lo_word(), \
tile.Top_Tile_cpu_dpath__rf_waddr.lo_word(), tile.Top_Tile_cpu_dpath__rf_wdata.lo_word(), tile.Top_Tile_cpu_dpath__rf_wen.lo_word(), tile.Top_Tile_core_dpath__rf_waddr.lo_word(), tile.Top_Tile_core_dpath__rf_wdata.lo_word(), tile.Top_Tile_core_dpath__rf_wen.lo_word(),
wb_reg_raddr1, wb_reg_rs1, wb_reg_raddr2, wb_reg_rs2, wb_reg_inst, wb_inst_str); wb_reg_raddr1, wb_reg_rs1, wb_reg_raddr2, wb_reg_rs2, wb_reg_inst, wb_inst_str);
} }
@ -179,7 +179,7 @@ int main(int argc, char** argv)
str[pos] = 0; \ str[pos] = 0; \
fputs(str, vcdfile); \ fputs(str, vcdfile); \
} while(0) } while(0)
dump_disasm(tile.Top_Tile_cpu_dpath__id_inst.lo_word(), "NDISASM_ID"); dump_disasm(tile.Top_Tile_core_dpath__id_inst.lo_word(), "NDISASM_ID");
dump_disasm(ex_reg_inst, "NDISASM_EX"); dump_disasm(ex_reg_inst, "NDISASM_EX");
dump_disasm(mem_reg_inst, "NDISASM_MEM"); dump_disasm(mem_reg_inst, "NDISASM_MEM");
@ -196,10 +196,10 @@ int main(int argc, char** argv)
mem_reg_inst = ex_reg_inst; mem_reg_inst = ex_reg_inst;
mem_reg_raddr1 = (mem_reg_inst >> 22) & 0x1f; mem_reg_raddr1 = (mem_reg_inst >> 22) & 0x1f;
mem_reg_raddr2 = (mem_reg_inst >> 17) & 0x1f; mem_reg_raddr2 = (mem_reg_inst >> 17) & 0x1f;
mem_reg_rs1 = tile.Top_Tile_cpu_dpath__ex_reg_rs1.lo_word(); mem_reg_rs1 = tile.Top_Tile_core_dpath__ex_reg_rs1.lo_word();
mem_reg_rs2 = tile.Top_Tile_cpu_dpath__ex_reg_rs2.lo_word(); mem_reg_rs2 = tile.Top_Tile_core_dpath__ex_reg_rs2.lo_word();
ex_reg_inst = tile.Top_Tile_cpu_dpath__id_inst.lo_word(); ex_reg_inst = tile.Top_Tile_core_dpath__id_inst.lo_word();
tile.clock_hi(LIT<1>(0)); tile.clock_hi(LIT<1>(0));
trace_count++; trace_count++;

2
riscv-rocket

@ -1 +1 @@
Subproject commit 7f318488d94b70f509f1ca6b9165d2aadcf5401c Subproject commit 1c8c7d1770c71e91ec8e97e89bf3637bf2f2d9ef

6
src/main/scala/RocketChip.scala
View File

@ -208,8 +208,10 @@ class Top extends Component {
val tl = uncore.io.tiles(i) val tl = uncore.io.tiles(i)
val ic = ICacheConfig(128, 2, co) val ic = ICacheConfig(128, 2, co)
implicit val rconf = RocketConfiguration(NTILES, co, ic) val dc = DCacheConfig(128, 4, co,
val tile = new Tile(resetSignal = hl.reset) nmshr = 2, nrpq = 16, nsdq = 17)
val rc = RocketConfiguration(NTILES, co, ic, dc)
val tile = new Tile(resetSignal = hl.reset)(rc)
tile.io.host.reset := Reg(Reg(hl.reset)) tile.io.host.reset := Reg(Reg(hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req) tile.io.host.pcr_req <> Queue(hl.pcr_req)