riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge pull request #931 from freechipsproject/fix-ram-model-source-reuse

Browse Source 
Fix ram model source reuse
This commit is contained in:
Wesley W. Terpstra 2017-08-07 16:56:13 -07:00 committed by GitHub
commit e27072e063
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
regression/Makefile
View File

@ -58,7 +58,7 @@ endif
ifeq ($(SUITE),UnittestSuite) ifeq ($(SUITE),UnittestSuite)
PROJECT=freechips.rocketchip.unittest PROJECT=freechips.rocketchip.unittest
CONFIGS=TLSimpleUnitTestConfig TLWidthUnitTestConfig CONFIGS=AMBAUnitTestConfig TLSimpleUnitTestConfig TLWidthUnitTestConfig
endif endif
ifeq ($(SUITE), JtagDtmSuite) ifeq ($(SUITE), JtagDtmSuite)

2
src/main/scala/tilelink/RAMModel.scala
View File

@ -223,7 +223,7 @@ class TLRAMModel(log: String = "")(implicit p: Parameters) extends LazyModule
val d_inc = d_inc_bytes.map(_ + d_inc_tree) val d_inc = d_inc_bytes.map(_ + d_inc_tree)
val d_dec = d_dec_bytes.map(_ + d_dec_tree) val d_dec = d_dec_bytes.map(_ + d_dec_tree)
val d_shadow = shadow.map(_.read(d_addr_hi)) val d_shadow = shadow.map(_.read(d_addr_hi))
val d_valid = valid(d.source) val d_valid = valid(d.source) holdUnless d_first
// CRC check // CRC check
val d_crc_reg = Reg(UInt(width = 16)) val d_crc_reg = Reg(UInt(width = 16))