riscv/rocket-chip
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jtag_dtm: Update regression to run and pass.

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This commit is contained in:
Megan Wachs
2017-01-18 12:08:13 -08:00
parent 1b31dfa700
commit e22b01a6fa
3 changed files with 12 additions and 7 deletions
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6
src/main/scala/rocketchip/ExampleTop.scala
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@ -30,7 +30,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _
class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
with PeripheryBootROM
with PeripheryDTM
with PeripheryDebug
with PeripheryCounter
with HardwiredResetVector
with RocketPlexMaster {
@ -39,14 +39,14 @@ class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer)
with PeripheryBootROMBundle
with PeripheryDTMBundle
with PeripheryDebugBundle
with PeripheryCounterBundle
with HardwiredResetVectorBundle
with RocketPlexMasterBundle
class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
with PeripheryBootROMModule
with PeripheryDTMModule
with PeripheryDebugModule
with PeripheryCounterModule
with HardwiredResetVectorModule
with RocketPlexMasterModule

6
src/main/scala/rocketchip/TestHarness.scala
View File

@ -26,7 +26,11 @@ class TestHarness()(implicit p: Parameters) extends Module {
}
}
val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug, io.success)
if (!p(IncludeJtagDTM)) {
val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug.get, io.success)
} else {
val jtag = Module(new JTAGVPI).connect(dut.io.jtag.get, reset, io.success)
}
val mmio_sim = Module(LazyModule(new SimAXIMem(4096)).module)
mmio_sim.io.axi4 <> dut.io.mmio_axi4