updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
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@ -2,7 +2,6 @@ package rocket
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import Chisel._
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import Chisel._
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import Constants._
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import Constants._
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import hwacha.GenArray
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class HubMemReq extends Bundle {
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class HubMemReq extends Bundle {
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val rw = Bool()
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val rw = Bool()
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@ -205,18 +204,18 @@ class CoherenceHubNoDir extends CoherenceHub {
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}
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}
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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val busy_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val busy_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val addr_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} }
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val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} }
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val tile_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val tile_xact_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
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val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
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val t_type_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
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val t_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
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val sh_count_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val sh_count_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val send_x_rep_ack_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val do_free_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_has_data_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_has_data_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_data_idx_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=log2up(NTILES))} }
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val p_rep_data_idx_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=log2up(NTILES))} }
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val rep_cnt_dec_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
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val rep_cnt_dec_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
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for( i <- 0 until NGLOBAL_XACTS) {
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for( i <- 0 until NGLOBAL_XACTS) {
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busy_arr.write( UFix(i), trackerList(i).io.busy)
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busy_arr.write( UFix(i), trackerList(i).io.busy)
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@ -243,7 +242,7 @@ class CoherenceHubNoDir extends CoherenceHub {
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val t = trackerList(i).io
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val t = trackerList(i).io
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conflicts(i) := t.busy(i) && coherenceConflict(t.addr, init.bits.address)
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conflicts(i) := t.busy(i) && coherenceConflict(t.addr, init.bits.address)
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}
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}
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aborting(j) := (conflicts.orR || busy_arr.flatten().andR)
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aborting(j) := (conflicts.orR || busy_arr.toBits().andR)
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abort.valid := init.valid && aborting
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abort.valid := init.valid && aborting
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abort.bits.tile_xact_id := init.bits.tile_xact_id
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abort.bits.tile_xact_id := init.bits.tile_xact_id
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init.ready := aborting(j) || initiating(j)
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init.ready := aborting(j) || initiating(j)
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