riscv/rocket-chip
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Mask debug interrupts similarly to other interrupts (#847)

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This makes single-step exceptions higher-priority than debug interrupts.
This commit is contained in:
Andrew Waterman 2017-07-06 12:03:24 -07:00 committed by GitHub
parent 988caf5e34
commit e1cc0a0a0e
1 changed files with 2 additions and 7 deletions
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9
src/main/scala/rocket/CSR.scala
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@ -300,9 +300,10 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val read_mip = mip.asUInt & supported_interrupts
val pending_interrupts = read_mip & reg_mie
val d_interrupts = reg_debugint << CSR.debugIntCause
val m_interrupts = Mux(reg_mstatus.prv <= PRV.S || (reg_mstatus.prv === PRV.M && reg_mstatus.mie), pending_interrupts & ~reg_mideleg, UInt(0))
val s_interrupts = Mux(m_interrupts === 0 && (reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie)), pending_interrupts & reg_mideleg, UInt(0))
val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(s_interrupts, m_interrupts))
val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(s_interrupts, m_interrupts, d_interrupts))
val interruptMSB = BigInt(1) << (xLen-1)
val interruptCause = UInt(interruptMSB) + whichInterrupt
io.interrupt := anyInterrupt && !reg_debug && !io.singleStep || reg_singleStepped
@ -310,12 +311,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
io.bp := reg_bp take nBreakpoints
io.pmp := reg_pmp.map(PMP(_))
// debug interrupts are only masked by being in debug mode
when (Bool(usingDebug) && reg_debugint && !reg_debug) {
io.interrupt := true
io.interrupt_cause := UInt(interruptMSB) + CSR.debugIntCause
}
val isaMaskString =
(if (usingMulDiv) "M" else "") +
(if (usingAtomics) "A" else "") +