riscv/rocket-chip
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fix small typos in README

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Scott Beamer
2014-08-14 17:59:24 -07:00
parent d3a8a224fe
commit e1a4d12c65
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README.md
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@@ -58,7 +58,7 @@ And to run the assembly tests on the C simulator and generate waveforms:
$ make run-vecasm-timer-tests-debug
$ make run-bmarks-test-debug
To FPGA-synthesizable verilog (output will be in `/fpga/generated-src`):
To get FPGA-synthesizable verilog (output will be in `fpga/generated-src`):
$ cd fpga/build/syn
$ make