riscv/rocket-chip
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Fix zscale testing

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Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
This commit is contained in:
Andrew Waterman
2015-12-01 17:31:10 -08:00
parent 5eeb8969f6
commit e0d849fec5
5 changed files with 15 additions and 2 deletions
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12
csrc/vcs_main.ZscaleTestHarness.cc Normal file
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@@ -0,0 +1,12 @@
// See LICENSE for license details.
extern "C" {
extern int vcs_main(int argc, char** argv);
int main(int argc, char** argv)
{
return vcs_main(argc, argv);
}
}

0
csrc/vcs_main.cc → csrc/vcs_main.rocketTestHarness.cc
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2
fsim/Makefrag
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@@ -15,7 +15,7 @@ sim_vsrcs = \
# C sources # C sources
sim_csrcs = \ sim_csrcs = \
$(base_dir)/csrc/vcs_main.cc \ $(base_dir)/csrc/vcs_main.$(TB).cc \
$(base_dir)/csrc/mm.cc \ $(base_dir)/csrc/mm.cc \
$(base_dir)/csrc/mm_dramsim2.cc \ $(base_dir)/csrc/mm_dramsim2.cc \

1
src/main/scala/Configs.scala
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@@ -277,6 +277,7 @@ class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache
class WithZscale extends Config( class WithZscale extends Config(
(pname,site,here) => pname match { (pname,site,here) => pname match {
case XLen => 32 case XLen => 32
case UseFPU => false
case BuildZscale => { case BuildZscale => {
TestGeneration.addSuites(List(rv32ui("p"), rv32um("p"))) TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
TestGeneration.addSuites(List(zscaleBmarks)) TestGeneration.addSuites(List(zscaleBmarks))

2
vsim/Makefrag
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@@ -14,7 +14,7 @@ sim_vsrcs = \
# C sources # C sources
sim_csrcs = \ sim_csrcs = \
$(base_dir)/csrc/vcs_main.cc \ $(base_dir)/csrc/vcs_main.$(TB).cc \
$(base_dir)/csrc/mm.cc \ $(base_dir)/csrc/mm.cc \
$(base_dir)/csrc/mm_dramsim2.cc \ $(base_dir)/csrc/mm_dramsim2.cc \