riscv/rocket-chip
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clint: use RegField.toBytes to save some work

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This commit is contained in:
Wesley W. Terpstra 2017-10-10 17:22:15 -07:00
parent 10472b4296
commit e094b94ce5
1 changed files with 7 additions and 13 deletions
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20
src/main/scala/devices/tilelink/Clint.scala
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@ -21,7 +21,7 @@ object ClintConsts
def timecmpBytes = 8 def timecmpBytes = 8
def size = 0x10000 def size = 0x10000
def timeWidth = 64 def timeWidth = 64
def regWidth = 32 def ipiWidth = 32
def ints = 2 def ints = 2
} }
@ -57,15 +57,11 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
val rtcTick = Bool(INPUT) val rtcTick = Bool(INPUT)
}) })
val time = Seq.fill(timeWidth/regWidth)(Reg(init=UInt(0, width = regWidth))) val time = RegInit(UInt(0, width = timeWidth))
when (io.rtcTick) { when (io.rtcTick) { time := time + UInt(1) }
val newTime = time.asUInt + UInt(1)
for ((reg, i) <- time zip (0 until timeWidth by regWidth))
reg := newTime >> i
}
val nTiles = intnode.out.size val nTiles = intnode.out.size
val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) } val timecmp = Seq.fill(nTiles) { Reg(UInt(width = timeWidth)) }
val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) } val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }
val (intnode_out, _) = intnode.out.unzip val (intnode_out, _) = intnode.out.unzip
@ -84,12 +80,10 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
* bffc mtime hi * bffc mtime hi
*/ */
def makeRegFields(s: Seq[UInt]) = s.map(r => RegField(regWidth, r))
node.regmap( node.regmap(
0 -> makeRegFields(ipi), 0 -> ipi.map(r => RegField(ipiWidth, r)),
timecmpOffset(0) -> makeRegFields(timecmp.flatten), timecmpOffset(0) -> timecmp.flatMap(r => RegField.bytes(r, timeWidth/8)),
timeOffset -> makeRegFields(time)) timeOffset -> RegField.bytes(time, timeWidth/8))
} }
} }