riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: use the fancy new hasData functions

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-09-02 20:10:40 -07:00
parent 11b0272d91
commit e034775bfa
2 changed files with 15 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
uncore/src/main/scala/tilelink2/Fragmenter.scala
View File

@ -134,15 +134,6 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
val in = io.in(0)
val out = io.out(0)
// Do there exist A messages with Data? (we don't count Arithmetic, because it is never fragmented)
val aDataYes = manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportGet || manager.anySupportHint
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportLogical
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else manager.maxTransfer
@ -156,10 +147,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
val dFirst = acknum === UInt(0)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Ceil(maxDownSize))
// It is important to optimize this to a constant if we know certain operaitons
// will never exist. This allows synthesis to eliminate the Muxes.
val dHasData = if (!dDataYes) Bool(false) else if (!dDataNo) Bool(true) else out.d.bits.hasData()
val dHasData = node.edgesOut(0).hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
@ -222,9 +210,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Ceil(maxDownSize))
// Statically optimize the case where hasData is a constant
val aHasData = if (!aDataYes) Bool(false) else if (!aDataNo) Bool(true) else out.a.bits.hasData()
val aHasData = node.edgesIn(0).hasData(in.a.bits)
val aMask = Mux(aHasData, UInt(0), aFragOH1)
val gennum = RegInit(UInt(0, width = counterBits))

14
uncore/src/main/scala/tilelink2/Narrower.scala
View File

@ -32,7 +32,7 @@ class TLNarrower(innerBeatBytes: Int) extends LazyModule
val maskSlices = Vec.tabulate (ratio) { i => in.mask()((i+1)*outerBeatBytes -1, i*outerBeatBytes) }
val filter = Reg(UInt(width = ratio), init = SInt(-1, width = ratio).asUInt)
val mask = maskSlices.map(_.orR)
val hasData = in.hasData()
val hasData = edge.hasData(in)
// decoded_size = 1111 (for smallest), 0101, 0001 (for largest)
val sizeOH1 = UIntToOH1(in.size(), log2Ceil(innerBeatBytes)) >> log2Ceil(outerBeatBytes)
@ -46,10 +46,13 @@ class TLNarrower(innerBeatBytes: Int) extends LazyModule
when (!hasData) { filter := SInt(-1, width = ratio).asUInt }
}
if (edge.staticHasData(in) == Some(false)) {
(Bool(true), UInt(0), UInt(0))
} else {
val select = Cat(mask.reverse) & new_filter
// !!! if never data
(last, Mux1H(select, dataSlices), Mux1H(select, maskSlices))
}
}
def merge(in: HasTLData, fire: Bool): (Bool, UInt) = {
val count = RegInit(UInt(0, width = log2Ceil(ratio)))
@ -57,7 +60,7 @@ class TLNarrower(innerBeatBytes: Int) extends LazyModule
val data = rdata << outerBeatBytes*8 | in.data()
val first = count === UInt(0)
val limit = UIntToOH1(in.size(), log2Ceil(innerBeatBytes)) >> log2Ceil(outerBeatBytes)
val last = count === limit || !in.hasData()
val last = count === limit || !edge.hasData(in)
val cases = Vec.tabulate (log2Ceil(ratio)+1) { i =>
val pow = 1 << i
Fill(1 << (ratio-i), data((pow+1)*outerBeatBytes*8-1, pow*outerBeatBytes*8))
@ -69,9 +72,12 @@ class TLNarrower(innerBeatBytes: Int) extends LazyModule
when (last) { count := UInt(0) }
}
// !!! if never data
if (edge.staticHasData(in) == Some(false)) {
(Bool(true), UInt(0))
} else {
(last, Mux1H(limit, cases))
}
}
val in = io.in(0)
val out = io.out(0)