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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.

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This commit is contained in:
Henry Cook
2016-09-14 17:43:07 -07:00
parent 3030718f72
commit e02d149cbe
8 changed files with 90 additions and 46 deletions
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9
src/main/scala/uncore/tilelink2/RegisterCrossing.scala
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@ -3,6 +3,7 @@
package uncore.tilelink2
import Chisel._
import chisel3.util.{Irrevocable, IrrevocableIO}
import junctions._
// A very simple flow control state machine, run in the specified clock domain
@ -24,8 +25,8 @@ class BusyRegisterCrossing(clock: Clock, reset: Bool)
// RegField should support connecting to one of these
class RegisterWriteIO[T <: Data](gen: T) extends Bundle {
val request = Decoupled(gen).flip()
val response = Decoupled(Bool()) // ignore .bits
val request = Irrevocable(gen).flip()
val response = Irrevocable(Bool()) // ignore .bits
}
// To turn on/off a domain:
@ -84,8 +85,8 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
// RegField should support connecting to one of these
class RegisterReadIO[T <: Data](gen: T) extends Bundle {
val request = Decoupled(Bool()).flip() // ignore .bits
val response = Decoupled(gen)
val request = Irrevocable(Bool()).flip() // ignore .bits
val response = Irrevocable(gen)
}
class RegisterReadCrossingIO[T <: Data](gen: T) extends Bundle {